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Fujitsu LOOX P70R: A Tablet For $2,000

Elpida Memory Samples 80nm 2Gbit DDR2 SDRAM

IBM To Release Power Specs To Researchers, Academia

NEC's Technology Enables Automatic Parallelization Of Applications

Fujitsu LOOX P70R: A Tablet For $2,000

The family of Fujitsu LOOX portables was extended with a new LOOX P70R tablet expected to go on sale in mid-January 2006 for about $2,000.

This novelty (supposedly named LIFEBOOK FMV-P8210) bases on Pentium M 753 ULV (1.2GHz), Intel 915GMS, 8.9" 1024x600 touchscreen, 512MB RAM, 30GB HDD, and is supplied with an external DVD-ROM/CD-RW.

Sized 232x167x34.5mm, the device weighs 990g. Interfaces include PCMCIA Type 2, SD, 2 x USB 2.0, Ethernet, IEEE802.11a/b/g, modem and mini-VGA. The claimed operation time is about 4 hours.

Source: PC Watch

Elpida Memory Samples 80nm 2Gbit DDR2 SDRAM

Elpida Memory today announced the shipment of 80nm-based 2Gbit DDR2 SDRAM samples. These samples are among the first 80 nm-based devices in the world to be shipped for customer evaluation, and the devices are expected to be used first in high-density memory modules for high performance servers.

The 2 Gigabit DDR2 SDRAM devices are available in three different data rate speeds: 533 Mega bits per second (Mbps), 667 Mbps, or 800 Mbps. They are organized as either 64 M words x 4 bits x 8 banks or as 32 M words x 8 bits x 8 banks. The supply voltage (VDD) is 1.8V+/-0.1V, and the operating temperature range (Tc) is 0 to 85C. The devices are available in 68-ball FBGA packages for easy mounting on Dual In-line Memory Modules (DIMMs).

Elpida's 2Gbit DDR2 SDRAM devices are currently available to customers as samples and volume production will begin in accordance with market demand.

Source: Elpida Memory

IBM To Release Power Specs To Researchers, Academia

IBM announced plans to provide free access for researchers and educational institutions to the specifications for its PowerPC 405 chip core. The move is yet one more way in which IBM is trying to widen the number of users of its Power processors. The hope is that allowing third parties to experiment with the PowerPC chip core will result in more innovation around the technology.

Cores are individual chip designs that developers can integrate with other designs to create custom chips. The announcement comes after academics engaged in collaborative multicore processing research approached IBM to request more access to its Power architecture, the vendor said in a release issued late Wednesday.

The researchers included the Research Accelerator for Multiple Processors (RAMP), a project headed up by the University of California, Berkeley; Stanford University; the Massachusetts Institute of Technology; Carnegie Mellon University (CMU); the University of Texas at Austin; and the University of Washington. Its aim is to build a scalable, multiboard system based on field programmable gate arrays so researchers can experiment with building, programming and managing massively parallel systems of between 64 and 1,024 processors.

IBM plans to make the PowerPC 405 specifications available to researchers and academics via Power.org, the vendor consortium it set up just over a year ago.

Also, last week, Sun Microsystems announced its intention to publish the specifications for its new UltraSparc T1 chip under a program called OpenSparc. Sun positions its UltraSparc-based servers against IBM's Power5+-based servers.


NEC's Technology Enables Automatic Parallelization Of Applications

NEC today announced that it has developed a multicore processor technology capable of performing automatic parallelization of application programs, without modifying them.

Key features:

  • An automatic parallelizing compiler, capable of effective extraction of parallelism from an application program utilizing its profile information.
  • An additional instruction set, designed to minimize parallelization overheads.
  • Processor architecture, which efficiently handles speculative execution.
  • Implementation realized by a simple extension to conventional processors.

The distinctive feature of this new technology is the ability of the automatic parallelizing compiler that utilizes profile information to aggressively exploit parallelization patterns, which are effective for accelerating the speed of application programs. In addition, although the parallelization is speculative, the speculation is almost always completely accurate. The speculation hardware works as a safety net by handling any rare misses, guaranteeing the correctness of the execution. This ensures that the compiler is not conservative in decisions concerned with these cases, resulting in an increase in the amount of parallelism exploited. The parallelism exploitation is supported by the speculative execution hardware that realizes efficient handling of detection of incorrect execution orders caused by the parallel execution of the program parts, cancellation of the incorrectly executed part, and re-execution of it. Moreover, the parallelization process can be performed in a practical period of time.

NEC has succeeded in operating this technology on a field-programmable gate array (FPGA). Moreover, its implementation has confirmed that only a marginal hardware extension is required and that application program speed is actually accelerated.

Source: NEC

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