AMD Introduces SSE5 x86 Instruction Set
AMD today introduced SSE5 (Streaming SIMD Extensions 5), a new extension of the x86 instruction set that is designed to allow software developers to simplify code and achieve greater efficiency for performance-hungry applications.
According to the press release, SSE5 helps maximize the output of each instruction and consolidates code base by introducing functionality previously only found in specialized, high-performance architectures, to the x86 platform:
- 3-Operand Instructions - a computing instruction is executed by applying a mathematical or logical function to operands, or inputs. By increasing the number of operands an x86 instruction can handle from 2 to 3, SSE5 enables the consolidation of multiple, simple instructions into a single, more effective instruction.
- Fused Multiply Accumulate - the 3-Operand Instruction capability enables the creation of new instructions which efficiently execute complex calculations. The Fused Multiply Accumulate instruction combines multiplication and addition to enable iterative calculations with one instruction. The simplification of the code enables rapid execution for more realistic graphics shading, rapid photographic rendering, spatialized audio, complex vector mathematics and other performance-intense applications.
The SSE5 specification, which is being made available to the developer community today at http://developer.amd.com/SSE5, will be implemented in products based on AMD’s next-generation "Bulldozer" core, available in 2009.
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