IDF San Francisco: Features Of New Micro-architecture
Having taken a look at processors, let´s pay some attention to their micro-architecture as well:
First, there´s a more powerful out-of-order engine featuring 4 channels, larger buffers and 14-stage pipeline.
Then, there´s lower power consumption, of which we have already written.
Third, the organization of L1 and L2 caches interaction in multi-core processors. In particular, direct data transfers between L1 caches of different cores. L2 cache will be shared and scalable. The bandwidth between L2 cache and core is to be increased.
Finally, prefetch and memory disambiguation are to be honed as well.
Source: Our reporter at IDF
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