VIA to announce three new Mini-ITX solutions along with new VIA Mark project
According to the fresh roadmap of VIA Technologies, in the nearest future it’s to present new original EPIA Mini-ITX solutions. At least, three new boards will be showcased at CeBIT 2003.
EPIA-M2 Mini-ITX, C3/Eden, 133MHz FSB, CLE266 (int. graphics, up to 64Mb allocated memory) + VT8235, DIMM socket (up to 1Gb DDR266), PCI slot, 2 õ ATA133, 6 õ USB2.0, 2 õ IEEE1394, TV-out, 6-ch. sound, 10/100 LAN, I/O Bracket, LVDS, Card bus/CF. As you can see EPIA-M2 differs from EPIA-M by Card bus/CF interface and integrated LVDS allowing to locate almost entire system in an LCD display.
EPIA-CL Mini-ITX, C3/Eden, 133MHz FSB, CLE266 (int. graphics, up to 64Mb allocated memory) + VT8235, DIMM socket (up to 1Gb DDR266), PCI slot, 2 õ ATA133, 6 õ USB2.0, 2-ch. sound, 2 õ 10/100 LAN, I/O Bracket, 4 serial ports. EPIA-CL has fewer multimedia features, but features dual LAN and 4 COM ports being a fine choice for an inexpensive POS terminal it’s designed for.
EPIA-P4 Mini-ITX, P4, 400/533MHz FSB, HT support (!),P4N266A (int. graphics, up to 32Mb allocated memory) + VT8235, DIMM socket (up to 1Gb DDR266), PCI slot, 2 õ ATA133, 6 õ USB2.0, IEEE1394, TV-out, 6-ch. sound, 10/100 LAN, I/O Bracket, LVDS. EPIA-P4 is a complete solution for the newest P4 processors. Besides, the P4N266A Northbridge is marked "N" that stands for low-power mobile design, according to VIA.
I’d also like to mention VIA’s processor roadmap. We’ve already used to discrete C3 and embedded ESPx0000 EBGA lines. But this year VIA launches the absolutely new Mark project. The idea is to create an integrated solutions combining a processor core and a Northbridge. Maybe we’ll see some prototypes next year, but this is only a guess.
As for Mark’s internals, it will naturally feature Nehemiah core, but the structure will be closer to Matthew than to C3 architecture. These are actually all details about VIA’s new project. And one more thing to stress: developing Mark, the company doesn’t pursue any speed records. The aim is to make this integrated solution work with passive cooling. Southbridge integration will be the next stage of the Mark project.
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