Super Talent, a manufacturer of flash storage solutions and DRAM memory modules, released new CFast storage cards.
Super Talent CFast storage cards are an evolution of traditional CompactFlash cards that have been in the industry for over 14 years. CFast has a bandwidth of 375MB/s -- 4 times more than offered by the fastest high-speed 600x (90MB/s) CompactFlash cards -- at the same original CF form factor. The new CFast storage card breaks the speed bottleneck between the SSD and the device by using a SATA interface. Super Talent has clocked these CFast cards at up to 200MB/sec read speeds.
Measuring 36.4 x 42.8 x 3.3 mm (Type I) and 36.4 x 42.8 x 5.0 mm (Type II) -- the same physical dimensions as those of CompactFlash cards, a CFast card has a single-chip controller and a flash memory module. The SATA interface consists of a 7-pin signal connector and a 17-pin power and control connector. The card operates at 3.3V.
Super Talent is offering five different CFast storage cards: 8GB and 16GB based on SLC (Single-Level Cell) flash, and 8GB, 16GB, 32GB based on MLC (Multi-Level Cell) flash.
Source: Super Talent
The Standard Performance Evaluation Corp. (SPEC) has released SPECjEnterprise2010, a new benchmark that measures full-system performance for Java Enterprise Edition (Java EE) application servers, databases and supporting infrastructure.
SPECjEnterprise2010 was developed by SPEC's Java subcommittee, which includes AMD, HP, IBM, Intel, Oracle, Red Hat, SAP, and Sun Microsystems.
SPECjEnterprise2010 includes a real-world workload and features that stress the capabilities of Java EE 5 or later application servers, databases, and supporting software infrastructure and hardware systems.
The new benchmark tests performance for a representative Java EE application and each of the components that make up the application environment, including hardware, application server software, JVM software, database software, JDBC drivers, and the system network. For the first time in a standardized benchmark, SPECjEnterprise2010 quantifies performance for the web services interface and JPA ORM engines.
The SPECjEnterprise2010 workload emulates information flow among an automotive dealership, manufacturing domain, supply chain management, and an order/inventory system. Load drivers in SPECjEnterprise2010 access the application through a web layer (HTML/HTTP) for the automotive dealership and through web services and Enterprise Java Beans (EJBs) for the manufacturing domain.
Performance is measured by a metric called EjOPS (jEnterprise Operations Per Second). The metric is derived by adding the operations per second in the dealer domain to the work orders per second in the manufacturing domain.
SPECjEnterprise2010 is available immediately from SPEC for $2,000.
Samsung Electronics today announced the availability of I8910 HD (Omnia HD, GT-I8910) Gold Edition. This premium version of the touchscreen smartphone features a luxurious new look inlayed with gold and a package of special accessories.
The special edition comes in two fashionable colors -- Champagne Gold and Luxury Brown -- both of which are inlayed with 24-karat gold. The Gold Edition package also includes a leather case and special accessories, including a mini-cradle and a TV-out cable.
Obviously, the actual specifications are the same.
The Samsung I8910 HD Gold Edition will be available beginning this month in selected markets including Singapore, Germany and the Middle East.
Source: Samsung Electronics
Micron Technology announced its RealSSD C300 SSD, claimed to be the industry's fastest notebook and desktop PCs. The novelty has native support for the next generation high-speed interface SATA 6Gb/s.
The C300 SSD leverages the SATA 6Gb/s interface to achieve a read throughput speed of up to 355MB/s and a write throughput speed of up to 215MB/s. Using the common PC Mark Vantage scoring system, the C300 SSD turns in a score of 45,000 from the HDD Suite.
The RealSSD C300 drive also leverages Micron's established 34nm MLC NAND flash memory. Micron's 34nm MLC NAND supports the high-speed ONFI 2.1 standard, ensuring the NAND performance keeps pace with the faster SATA 6Gb/s interface.
The drives will be available in 1.8-inch and 2.5-inch form factors, with 128GB and 256GB capacities. Micron is currently sampling the C300 SSD in limited quantities and expects to enter production in Q1'2010.
Source: Micron Technology
GlacialTech, a provider of cooling, power supply, and PC enclosure solutions, announced the launch of GlacialStars brand. The new brand addresses the mainstream and entry-level markets, offering affordable CPU coolers, case fans, NB coolers, thermal compounds and the like.
Compared to other similar products, GlacialStars solution are claimed to be better in terms of noise reduction, performance, and weight.
P.S. Apparently, the Glacialstars brand has its own website http://www.glacialstars.com/, but it hasn't been updated with new offerings yet. Three products that are present at the website (a CPU cooler, a PSU, and a case fan) are all dated 2008.
Researchers from Intel Labs demonstrated an experimental, 48-core Intel processor, or "single-chip cloud computer," that rethinks many of the approaches used in today's designs for laptops, PCs and servers. This futuristic chip boasts about 10 to 20 times the processing engines inside today's most popular Intel Core-branded processors.
The long-term research goal is to add incredible scaling features to future computers that spur entirely new software applications and human-machine interfaces. The company plans to engage industry and academia next year by sharing 100 or more of these experimental chips for hands-on research in developing new software applications and programming models.
While Intel will integrate key features in a new line of Core-branded chips early next year and introduce six- and eight-core processors later in 2010, this prototype contains 48 fully programmable Intel processing cores, the most ever on a single silicon chip. It also includes a high-speed on-chip network for sharing information along with newly invented power management techniques that allow all 48 cores to operate extremely energy efficiently at as little as 25 watts, or at 125 watts when running at maximum performance (about as much as today's Intel processors and just two standard household light bulbs).
Intel plans to gain a better understanding of how to schedule and coordinate the many cores of this experimental chip for its future mainstream chips. For example, future laptops with processing capability of this magnitude could have "vision" in the same way a human can see objects and motion as it happens and with high accuracy.
Imagine, for example, someday interacting with a computer for a virtual dance lesson or on-line shopping that uses a future laptop's 3-D camera and display to show you a "mirror" of yourself wearing the clothes you are interested in. Twirl and turn and watch how the fabric drapes and how the color complements your skin tone.
This kind of interaction could eliminate the need of keyboards, remote controls or joysticks for gaming. Some researchers believe computers may even be able to read brain waves, so simply thinking about a command, such as dictating words, would happen without speaking.
Intel Labs has nicknamed this test chip a "single-chip cloud computer" because it resembles the organization of datacenters used to create a "cloud" of computing resources over the Internet, a notion of delivering such services as online banking, social networking and online stores to millions of users.
Cloud datacenters are comprised of tens to thousands of computers connected by a physically cabled network, distributing large tasks and massive datasets in parallel. Intel's new experimental research chip uses a similar approach, yet all the computers and networks are integrated on a single piece of Intel 45nm, high-k metal-gate silicon about the size of a postage stamp, dramatically reducing the amount of physical computers needed to create a cloud datacenter.
The concept chip features a high-speed network between cores to efficiently share information and data. This technique gives significant improvement in communication performance and energy efficiency over today's datacenter model, since data packets only have to move millimeters on chip instead of tens of meters to another computer system.
Application software can use this network to quickly pass information directly between cooperating cores in a matter of a few microseconds, reducing the need to access data in slower off-chip system memory. Applications can also dynamically manage exactly which cores are to be used for a given task at a given time, matching the performance and energy needs to the demands of each.
Related tasks can be executed on nearby cores, even passing results directly from one to the next as in an assembly line to maximize overall performance. In addition, this software control is extended with the ability to manage voltage and clock speed. Cores can be turned on and off or change their performance levels, continuously adapting to use the minimum energy needed at a given moment.
Programming processors with multiple cores is a well-known challenge for the industry as computer and software makers move toward many-cores on a single silicon chip. The prototype allows popular and efficient parallel programming approaches used in cloud datacenter software to be applied on the chip. Researchers from Intel, HP and Yahoo's Open Cirrus collaboration have already begun porting cloud applications to this 48 IA core chip using Hadoop, a Java software framework supporting data-intensive, distributed applications as demonstrated by Rattner today.
Intel plans to build 100 or more experimental chips for use by dozens of industrial and academic research collaborators around the world with the goal of developing new software applications and programming models for future many-core processors.
This milestone represents the latest achievement from Intel's Tera-scale Computing Research Program, aimed at breaking barriers to scaling future chips to 10s-100s of cores. It was co-created by Intel Labs at its Bangalore (India), Braunschweig (Germany) and Hillsboro, Ore. (U.S.) research centers. Details on the chip's architecture and circuits are scheduled to be published in a paper at the International Solid State Circuits Conference in February.
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