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IDF Fall, day 1: Montecito

As we´ve already mentioned, the IDF Fall opening speech was focused on two trends: transition from MHz to parallelism and wireless networking intensification. This is how the first trend looks on the example of Montecito:

This processor has 1.72 billion transistors, 26.5 MB L3 cache. Each of two cores owns about 12 MB of cache, while the remaining 2.5 MB is dedicated for buffer needs. To improve parallelism efficiency Instruction Level Parallelism (ILP) Montecito has two new instructions, and a part of L2 is dedicated to instructions.

Besides ILP, the performance is optimized by thread switching using thread-level parallelism (TLP) to reduce fetch latencies.

Montecito developers are also focused on energy consumption. Max. dissipated heat is 100W, but CPU is able to increase voltage and clock (self-overclocking) or, vice versa, declock down to 70W.

Finally, another interesting technology SilverVale. It enables several OS to work simultaneously.

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