Intel: high-k dielectrics enable to reduce leakage currents by a factor of 100!

Already in 2007 Intel is going to use special high-k dielectrics in transistor gates that, according to specialists, will allow to reduce leakage currents by at least a factor of 100! According to Moore´s Law, the amount of transistors might reach a billion by that time. In 2007 the company plans to move to 45nm process technology. At that time the usual silicon dioxide will be replaced by a still undisclosed high-k dielectric. Alongside the company is going to stop using polycrystalline silicon additions during forming transistor gate electrodes and start using two different metals for NMOS and PMOS transistors.

Essentially the leakage problem is: the thickness of silicon dioxide layer used as dielectric is currently 5 atoms that results in electrons tunnelling through the oxide level in the enabled state and increases energy consumption. The transition to high-k materials makes the transistor current in the enabled state just slightly higher than in the disabled state. This naturally reduces leakages.

The leakage reduction effect of high-k oxides has been known for a long time, however scientists have been searching for suitable materials. The already known high-k materials like hafnium, zirconium, etc. oxides usually result in considerable channel current reduction under gate dielectrics and lead to serious problems of setting gate operate threshold voltage, especially in PMOS transistors.

More details on new high-k dielectric technologies are to be presented by Robert Chau, lead developer of Intel´s lab in Hillsboro, Oregon, on Thursday at International Gate Insulator Workshop in Tokyo. The presentation will describe the development of NMOS and PMOS transistors with 80nm gates and the usage of 1.4nm (14 Angstrom) dielectrics.

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