On February 21, the largest CPU giant Intel is expected to announce two new models of Pentium 4 processors. The first of them is the long-awaited 600 series of Pentium 4 processors (630, 640, 650, and 660) operating at frequencies from 3.0 to 3.6 GHz with 200 MHz system bus (800 MHz Quad Pumped Bus). They are based on the new revision of Prescott core supporting Extended Memory 64-bit Technology (EM64T, a counterpart of AMD x86-64) and Enhanced Intel SpeedStep. The second model is represented by a single model so far – Pentium 4 Extreme Edition, 3.73 GHz CPU clock, designed for 266 MHz system bus (1066 MHz Quad Pumped Bus). Note that it's actually the first extreme processor on Prescott core, announced by the company. Both models are equipped with 2 MB L2 Data Cache. This article reviews key features of the new Prescott core revisions used in both processors compared to the previous Prescott and Nocona core revisions, which were reviewed in the article "Detailed Platform Analysis in RightMark Memory Analyzer. Part 6 - Intel Xeon (Nocona) Platform».
Testbed Configurations and Software
We'll start the analysis of the new Prescott core revision with selected characteristics generated by the CPUID instruction.
Pentium 4 660
Among the most important distinctions, which distinguish the new Prescott core revision in the 600 series of Pentium 4 processors from the previous revision, one can note, first of all, the core stepping increase to 3 (the new cores have the 0F43h signature, the last E0 revision was characterized by the 0F41h signature). Taking into account that the manufacturer assigns a letter "of a higher rank" to the alpha-numeric designation of each next Prescott core revision without modifying the numeric index (revision C0 is followed by D0 and then E0), the new revision can presumably be referred to as F0, this designation will be used in this article. It'll be interesting to see whether it's actually true.
There is one noteworthy modification in the Cache/TLB descriptors, one of them is changed from 7Ch to 7Dh, which means an upgrade from 1 MB to 2 MB L2 Cache preserving its other characteristics (associativity and line size).
Nevertheless, the most interesting characteristics in our opinion are those of the key features of the new core revision. Aside from the support for Thermal Monitor 2 Nevertheless, the most interesting characteristics in our opinion are those of the key features of the new core revision. Aside from the support for Thermal Monitor 2 and Execute Disable bit (they were already included into the E0 revision of Prescott core, i.e. "J series" of Pentium 4 processors), the new core revision supports Enhanced Intel SpeedStep and EM64T, which are natively supported by server Nocona cores. It's interesting to note two currently "unknown" (i.e. not available in the official documentation) technologies, denoted by Bits 2 and 13 of the ECX register. Perhaps they will be used to denote those LaGrande and VanderPool technologies, which are currently "hidden" from regular users. We hope it'll become clear with the new revision of the document Intel(R) Processor Identification and the CPUID Instruction, Application Note 485, latest 027 revision is dated July 2004.
So, by all of the above-mentioned parameters the new revision of Prescott core can be actually considered a desktop incarnation of the latest E0 revision of the server Nocona core. Besides, it is equipped with two megabytes of L2 Cache. Let's proceed to the new extreme series of Pentium 4 processors.
Pentium 4 Extreme Edition 3.73 GHz
Where does its "extremity" lie? The answer to this question is absolutely not obvious. This processor lacks the traditional component of an extreme series – L3 Data Cache. However, no one promised that the "extremity" lies in L3 Cache. Moreover, that's not unexpected, taking into account that there is absolutely no use in 2 MB L3 Cache and inclusive organization of the Data Cache in the presence of 2 MB L2 Cache! (in case of the inclusive cache organization, the efficient volume of the cached space is equal to the volume of the largest cache, but not to the total volume of all cache levels). It's quite possible that the "extremity" means the core capacity to operate at 266 MHz of the FSB (which we didn’t manage to obtain with our first sample under review), because... there are just no other options.
Let's go on: CPUID signature in this model is again 0F43h, i.e. it's sort of the same new F0 revision of Prescott core, implemented in the 600 series of Pentium 4 processors. Nevertheless, there are obvious differences in features between those seemingly identical cores. For example, the extreme version... lacks Thermal Monitor 2 and Enhanced Intel SpeedStep. Nevertheless, it offers XD bit and EM64T, as well as the two "unknown" technologies, which we already mentioned above.
Thus, by CPUID characteristics the first extreme series of Prescott cores is quite an ambiguous phenomenon. Part of its technologies was obviously borrowed from the previous E0 revision of the extreme Prescott core (XD bit), and another part – from the server Nocona core (EM64T). But the whole point is that only part of them – for some reason the new extreme core was "deprived" of TM2 (from Prescott E0) and Enhanced Intel SpeedStep (from Nocona), which are available in the same revision of the non-extreme Prescott core (see above). It seems that the reasons are clear only to the CPU manufacturer, but it obviously managed to confuse users very well...
Real Bandwidth of Data Cache/Memory
Let's proceed to the RMMA rest results for the new processors. The general picture of the real throughput of memory system levels (L1/L2/RAM) in Pentium 4 660 and Pentium 4 EE 3.73 looks the same.
You can see the following key features on the graph: L2 Data Cache size has been actually increased to 2 MB. But the bandwidth of this memory system level slumps noticeably already at 256 KB blocks of data. This is connected with D-TLB buffer depletion, which size in the new core revision remains the same – 64 entries, i.e. 256 KB of the "covered" virtual address space. The lack of write efficiency differences between L1 and L2 caches (i.e. no typical inflection in the 16 KB area) indicates the Write-Through organization, when the data is always written to L2 Cache only, which increases the read efficiency of the small L1 Cache.
The quantitative characteristics of L1 Cache bandwidth are unchanged – they match those for previous Prescott and Nocona cores, D0 revision. L2 Cache bandwidth characteristics are somewhat different – in particular, you can see a tad higher read efficiency of this cache level in both processors (average L2 Cache bandwidth within the 20 – 240 KB range). Nevertheless, considering the substantial spread of this value within the specified range, it can hardly be considered a symptom of a thorough core revision – it's rather just a measurement error :).
Nevertheless, memory bandwidth values demonstrate noticeable changes – the real read bandwidth of this memory system level is noticeably higher. On the one hand, this may be due to the further improvement of the hardware prefetch algorithm, on the other hand – a consequence of using the new i925XE chipset, where the manufacturer probably managed a more efficient memory controller. Higher memory bandwidth values on Pentium 4 EE 3.73 can be explained by the 266 MHz FSB frequency (which increases its peak bandwidth up to 8.53 GB/sec) and the memory operating in FSB-synchronous mode (FSB:DRAM frequency ratio – 1:1).
Maximum Real Memory Bandwidth
As usual (for Pentium 4 processors), Software Prefetch method allows maximum memory bandwidth, while other methods are not so highly efficient.
Real memory bandwidth to software prefetch distance curves for Pentium 4 660 and Pentium 4 EE 3.73 match on the qualitative level – only quantitative indices are different, they are connected with different FSB frequencies (200 MHz in Pentium 4 660 versus 266 MHz in Pentium 4 EE 3.73). The obtained prefetch curves are typical of Prescott cores (in outward appearance they match with those we obtained for the previous revisions of this core). Besides, they indicate the lack of differences in software prefetch algorithms in non-extreme and extreme modifications of the new Prescott core F0 revision.
As for the maximum real memory write bandwidth, you can see that little has changed here – the use of forward write method allows to reach 2/3 of maximum theoretical FSB throughput in all cases. Efficiency of writing cache lines can also be considered practically the same in all cases: gains relative to the average memory write bandwidth amount for approximately 500 MB/sec.
Data Cache/Memory Latency
The overall picture of latency, as well as of memory bandwidth, in both processors looks the same.
Typical features of Data Cache and D-TLB organization are no less clear in this test: 16 KB and 2 MB inflections, which correspond to L1 and L2 Cache sizes, as well as smooth rise of random access latency in L2 Cache with the block size starting from 256 KB.
Quantitative latency characteristics of L1 and L2 Cache are the same for all processors included into the table. By the way, 4-cycle L1 latency in Pentium 4 EE 3.73 can be considered the first experimental verification of the fact, that this processor is really based on Prescott core (as is well known, all previous Pentium 4 Extreme Edition processors were based on Gallatin core, its L1 Cache latency was 2 cycles).
Concerning the memory latency, the table values have been obtained in a separate test, where the data chain is walked at 128 byte steps, i.e. the effective L2 Cache line size. Besides, for the first time we have published data obtained with disabled Hardware Prefetch for the new processors. This data illustrates its efficiency (the latest method for measuring memory latency on Pentium 4 platform is described in detail in our recent article "Two methods for measuring memory latency on Intel Pentium 4 platform in RightMark Memory Analyzer — how to choose the right one?").
Thus, memory latency in all walk modes decreased a little in comparison with the previously tested Pentium 4 platform (Prescott D0) – the latency drop is the most noticeable at random walk (about 20 ns), obviously due to the new i925XE chipset (because Hardware Prefetch at random walk is practically idle, as we have already told above and will see below). Note also that memory latency in Pentium 4 EE 3.73 is a tad lower – the most obvious explanation is in synchronous memory operation on this platform.
In both cases disabled Hardware Prefetch results in almost 2.5-fold latency increase of forward and backward walk, it's a tad lower (approximately by 1.5 times) in case of pseudo random walk and is practically imperceptible at random walk. The results obtained can be considered a direct evaluation of Hardware Prefetch at various memory access modes – it reaches maximum in case of forward and backward walks, a tad lower for pseudo random walk (as we have assumed, in this case prefetch operates on the level of whole memory pages); and finally, this algorithm is practically idle at random walk. Unfortunately, it's currently impossible to compare the results of hardware prefetch efficiency obtained on new Prescott core revision with the previous revisions – measuring memory latency without hardware prefetch is a new developing tendency in our research. From the quantitative positions, the "true" average latency of Corsair DDR2-533 modules (used in our tests) is 80.4 ns in asynchronous mode and 76.6 ns in synchronous mode. Lower latencies in backward walk mode with disabled Hardware Prefetch are an interesting but unexplainable fact.
Minimum Latency of Data Cache/Memory
Minimum latency of L2 Cache, Pentium 4 660 and Pentium 4 EE 3.73, Method 2
L1-L2 bus unload curves, i.e. minimum L2 latency, look the same for both processors and are quite typical of Prescott cores: latency of this level obviously does not reach its maximum at standard L1-L2 bus "unloading" by inserting "empty" operations (Method 1), and it goes down to 22 cycles at "non-standard" unloading, specially developed for processors with pronounced speculative data loading (Method 2).
"Standard" L2-RAM bus unloading curves for both processors are no different from the ones we previously obtained on Prescott and Nocona cores, D0 revision.
We should again note the decrease of memory access latency (in comparison with the previously reviewed Pentium 4 platform), which is practically imperceptible at forward and backward walks and maximum (20-25 ns) at random walk. Note that minimum memory access latency values are practically no different from the average values obtained in the previous test, except for the forward and backward walk modes, where hardware prefetch gets an additional advantage from unloading L2-RAM bus (BIU). This assertion certainly does not extend to measurements with disabled Hardware Prefetch.
Data Cache Associativity
L1/L2 D-Cache associativity test for both processors, which result is shown on the picture, indicates the lack of any changes in this parameter. As in all the other reviewed Pentium 4/Xeon processors, the "effective" L1 data cache associativity is equal to 1, associativity of the integrated L2 instruction cache/data cache – 8.
Real L1-L2 Cache Bus Bandwidth
Though the above quantitative characteristics (bandwidth, latency) of L1 and L2 D-Caches in the processors under review almost match the test results of previous Prescott and Nocona core revisions, the present test results open up new unexpected details on the L1-L2 bus design. Namely, you cannot fail to notice the further decrease of its efficiency to 45.3-45.8% for reading operations and up to 12.5-12.8% for writing operations (in good old times – i.e. Northwood core period, the efficiency of this bus utilization in reading operations used to be close to the theoretical maximum).
Trace Cache, Decode/Execute Efficiency
Let's examine another interesting component of the NetBurst microarchitecture – its specialized cache for micro-operations (Execution Trace Cache) provided by the predecoder. Assumptions about its size being increased to 16000 micro-operations and the introduction of quadruple prefetch of micro-operations per cycle (which started to circulate when server Nocona cores appeared) proved to be wrong again.
As always, the overall picture of decode/execute speed for "large" 6-byte CMP instructions is the most illustrative. In this test, as in all the other tests of this type, there are no qualitative changes in behaviour of Prescott cores under review. Let's proceed to the quantitative evaluation.
Decode/execute efficiency, Xeon (Nocona D0)
To track the general tendency of changes, let's provide the data obtained for Xeon (Nocona core, D0 revision) for a control point. This processor core, equipped with EM64T, was the first to show the deterioration tendency for decode/execute efficiency of some commands – in particular, simple operations like TEST (test eax, eax) and CMP 1 (cmp eax, eax). Let's see what changes this micro-architectural component suffered in the new Prescott core revision, which also supports EM64T.
Decode/Execute Efficiency, Pentium 4 660 and Pentium 4 EE 3.73 (Prescott F0)
Differences between these two processors are so insignificant, that we decided to publish the "mean" data in a single table. Alas, the CPU performance deterioration tendency (execution of some commands) is also active here – i.e. EM64T introduction costs dear. First of all, you can see the increasingly less efficient execution of TEST and CMP 1 – the execution speed of the former dropped to 1.71 instructions/cycle, of the latter – to 2.58 instructions/cycle. One can say that the latter dropped to the execution efficiency level of other CMP commands (2-5). The second significant modification, which again represents the new core revision in an unfavourable light, is the reduction of maximum decode/execute speed for all CMP operations from L2 Cache to 4.0 bytes/cycle (1.0 or 0.67 instructions/cycle, depending of the command size) as well as "prefix" CMP to 4.14 bytes/cycle (0.52 instructions/cycle).
The second significant efficiency deterioration of the decoder/pipeline in Nocona core with EM64T was in the decreased efficiency of truncating "meaningless" prefixes in the test that executed instructions of the type [0x66]nNOP, n = 0..14.
The new revision of Prescott cores with EM64T is no different in this respect, or the difference is insignificant: decreased execution speed of "prefix" NOPs with the increased number of prefixes in new Prescott processors almost coincides with the Nocona core (except for one additional, easily reproduced "slump" in case of 13 prefixes before the NOP instruction). Thus, the conclusion previously drawn about the first "64-bit" Nocona core also extends to the new "64-bit" revision of Prescott core: truncating extra prefixes, which is the function of the x86-instruction decoder located before Trace Cache, is less effective now. It's quite logical to assume that this concerns not only prefixes but the operation efficiency of the decoder on the whole.
We shall not go into the analysis of D-TLB and I-TLB characteristics, considering that they (by CPUID descriptors) match in all processors under review.
D-TLB size is 64 page entries (we have already seen that in the other test results), a miss penalty (when the TLB size is used up) costs a processor minimum 57 cycles. Associativity – full.
I-TLB size is 64 entries (this resource is divided in two between logical processors when Hyper-Threading is enabled), a miss penalty is 45 cycles (forward, backward walks) and more (random walk), associativity – full.
In our previous analysis of the NetBurst microarchitecture we marked one interesting but not so sunny – both to the manufacturer and to end users – tendency of this microarchitecture in every next implementation. This tendency lies in... gradual deterioration of low-level characteristics of the microarchitecture under review as it develops, i.e. introducing the increasing number of "bells and whistles". Remember, when we upgraded from Northwood to Prescott, together with SSE3 we "inherited" a significantly increased D-Cache latencies, noticeable reduction of the effective bandwidth of the L1-L2 bus, and finally decreased code execution efficiency. And the upgrade to the server modification of Prescott – the first x86-64-compatible Nocona core – resulted in a further execution speed reduction of some commands and the decreased decoder efficiency in general.
Alas, the conclusion that can be drawn by our today's test results will be very pessimistic: the above tendency... lives on. The new "64-bit" revision of Prescott core is characterized by further reduction of L1-L2 D-Cache bus throughput and of the execution speed of comparison operations.
What concerns the comparison of non-extreme and extreme versions of the new Prescott core revision, our tests demonstrate that their microarchitectures are completely identical. Thus, the same CPUID signature (0F43h) in both processors, despite some different features, is partially justified – this is indeed the same core. But in the first case (600 series Pentium 4) it operates with 200 MHz FSB, and it features (even "boasts of") TM2 and EIST technologies. And in the second case (Pentium 4 Extreme Edition 3.73 GHz – this processor hasn't got its number yet) the core can operate with 266 MHz FSB. TM2 and EIST technologies, which are certainly implemented in this core, are hidden well on the hardware level.
Note that Pentium 4 Extreme Edition 3.73 GHz is the first case (certainly, not an only one in future), when the CPU "extremity" is set by an increased FSB frequency instead of a large L3 D-Cache. But in such a case the "extremity" notion gets more than conventional – one can always try to find a better sample (than in our case) of the "non-extreme" Pentium 4 processor of the 600 series and make it work with 266 MHz FSB. In conclusion we want to note that such an approach to "extremity" may also indicate revocation of design and/or production of Potomac core (a counterpart of Prescott core with L3 D-Cache) – at least in the desktop sector (leaving the ground only to the server modifications with very large L3 Cache, which significantly surpasses the current 2 MB L2 Cache size).
Dmitry Besedin (email@example.com)
February 21, 2005
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