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DDR Memory Analysis. Part 1: Kingmax DDR-466

November 30, 2004



We proceed with the series of articles devoted to the low level analysis of the most important characteristics of memory modules using the RightMark Memory Analyzer test package. The object of our next analysis is a couple of colored Kingmax DDR-466 modules of the high-performance hardcore series with stylish original design.

Manufacturer Information

Module manufacturer: Kingmax Inc.
Chip manufacturer: Kingmax Inc.
Web site of the module manufacturer: http://www.kingmax.com/product/color.htm
Web site of the chip manufacturer: N/A

Module Appearance

Photo of the memory module




Photo of the memory chip




Part Numbering System of Modules and Chips




Module Part Number Expansion

Data sheet on Kingmax DDR-466 does not contain information about the expansion of some part numbers of the modules. The documentation provides only brief technical characteristics pertaining to some part numbers. The characteristics of the module under review are provided below.

Field Value Expansion
0 MPYB62D-38KS4G Module density: 256 Mb
Configuration: 32M x64
Module bandwidth: 3.7 GB/sec
Memory clock: 4.3 ns
Data rate: 466 MT/s
Timings (tCL-tRCD-tRP): 3.0-4-4

SPD module chip data

Description of the SPD general standard:
JEDEC Standard No. 21-C, 4.1.2 - SERIAL PRESENCE DETECT STANDARD, General Standard

Description of the SPD specific standard for DDR:
JEDEC Standard No. 21-C, 4.1.2.4 – Appendix D, Rev. 1.0: SPD’s for DDR SDRAM

Function Byte Value Expansion
Fundamental Memory Type 2 07h DDR SDRAM
Number of Row Addresses on this assembly 3 0Dh 13 (RA0-RA12)
Number of Column Addresses on this assembly 4 0Ah 10 (CA0-CA9)
Number of DIMM Banks 5 01h 1 physical bank
Data Width of this assembly 6, 7 40h, 00h 64 bit
Voltage Interface Level of this assembly 8 04h SSTL 2.5V
SDRAM Cycle time (tCK) at maximum supported CAS# latency (CL X) 9 43h 4.3 ns (232.5 MHz)
DIMM configuration type 11 00h Non-ECC
Refresh Rate/Type 12 82h 7.8125 ms – 0.5x reduced self-refresh
Primary SDRAM Width (organization type) of the memory module chips 13 08h x8
Error Checking SDRAM Width (organization type) of the memory chips in the ECC module 14 00h Not defined
Burst Lengths Supported (BL) 16 0Eh BL = 2, 4, 8
Number of Banks on SDRAM Device 17 04h 4
CAS Latency (CL) 18 18h CL = 2.5, 3.0
Minimum clock cycle (tCK) at reduced CAS latency (CL X-0.5) 23 50h 5.00 ns (200.0 MHz)
Minimum clock cycle (tCK) at reduced CAS latency (CL X-1.0) 25 00h Not defined
Minimum Row Precharge Time (tRP) 27 48h 18.0 ns
4.19, CL = 3.0
3.60, CL = 2.5
Minimum Row Active to Row Active delay (tRRD) 28 28h 10.0 ns
2.33, CL = 3.0
2.00, CL = 2.5
Minimum RAS to CAS delay (tRCD) 29 48h 18.0 ns
4.19, CL = 3.0
3.60, CL = 2.5
Minimum Active to Precharge Time (tRAS) 30 28h 40.0 ns
9.30, CL = 3.0
8.00, CL = 2.5
Module Bank Density 31 40h 256 MB
Minimum Active to Active/Refresh Time (tRC) 41 3Ch 60.0 ns
13.95, CL = 3.0
12.00, CL = 2.5
Minimum Refresh to Active/Refresh Command Period (tRFC) 42 46h 70.0 ns
16.28, CL = 3.0
14.00, CL = 2.5
Maximum device cycle time (tCKmax) 43 30h 12.0 ns
SPD Revision 62 00h Revision 0.0
Checksum for Bytes 0-62 63 AFh 175 (true)
Manufacturer’s JEDEC ID Code (only the first significant bytes are shown) 64-71 7Fh, 7Fh,
7Fh, 25h
Kingmax Semiconductor
Module Part Number 73-90 - MPYB62D-38KS4G-MAAR
Module Manufacturing Date 93-94 04h, 00h 2004
Module Serial Number 95-98 00h, 00h,
00h, 00h
Not defined

SPD chip contents look not quite standard. Supported CAS# Latency values – 3.0 and 3.0. The first value (CL X = 3.0) corresponds to the non-standard cycle time – 4.3 ns (nevertheless, it matches the value claimed in Kingmax specification), that is the module operates at about 233 MHz (DDR-466). Timing scheme for this case can be expressed as 3.0-4.2-4.2-9.3, in reality (taking into account that tRCD, tRP and tRAS cannot take non-integral values) – 3.0-4-4-9 (which again matches the values provided above in the part number expansion). The second value of CAS# latency (CL X-0.5 = 2.5) corresponds to the standard (for DDR-400) cycle time of 5.0 ns. Timing scheme in the second case is written as 2.5-3.6-3.6-8 (in reality – 2.5-4-4-8).

Dmitry Besedin (dmitri_b@ixbt.com)

November 30, 2004


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