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Memory Module Analysis.
Part 24: Corsair DDR2-800 Low-Latency Modules with EPP Support (XMS2-6400C3)

November 27, 2006



We proceed with the analysis of the most important characteristics of high-performance DDR2 memory modules using our RightMark Memory Analyzer. Today we are going to review a new offer from Corsair — high-speed DDR2-800 memory modules with SPD EPP support (Enhanced Performance Profiles) and extremely low latencies — 2GB dual-channel kit of XMS2-6400C3 memory modules.

Manufacturer Information

Module manufacturer: Corsair Memory
Manufacturer of module chips: unknown
Web site of the module manufacturer: http://www.corsairmemory.com/corsair/xms2.html

Module Exterior

Photo of the memory module

Module Part Number

Module Part Number Expansion

The manufacturer's web site does not publish the DDR2 Part Number expansion of XMS2-series memory modules. TWIN2X2048-6400C3 Specs run that this product is a kit of two modules, 2GB in total, based on sixteen 64M x 8 chips. These modules support the new open EPP standard (SPD extension), developed by Corsair and NVIDIA. It allows to configure memory modules for maximum performance automatically on motherboards that support this standard. The manufacturer guarantees operation of these modules in DDR2-800 mode with EPP 3-4-3-9-2T timings and 2.2 V voltage. But the default mode in the standard SPD section is the standard DDR2-800 mode with 5-5-5-18 timings.

SPD chip data

Description of the general SPD standard:

Description of the specific SPD standard for DDR2:

Parameter Byte Value Expansion
Fundamental Memory Type 2 08h DDR2 SDRAM
Number of Row Addresses on this assembly 3 0Eh 14 (RA0-RA13)
Number of Column Addresses on this assembly 4 0Ah 10 (CA0-CA9)
Number of DIMM Banks 5 61h 2 physical banks
Data Width of this assembly 6 40h 64 bit
Voltage Level 8 05h SSTL 1.8V
SDRAM Cycle time (tCK) at maximum supported CAS# latency (CL X) 9 25h 2.50 ns (400.0 MHz)
DIMM configuration type 11 00h Non-ECC
Refresh Rate/Type 12 82h 7.8125 ms — 0.5x reduced self-refresh
Primary SDRAM Width (organization type) of the memory module chips 13 08h x8
Error Checking SDRAM Width (organization type) of the memory chips in the ECC module 14 00h Not defined
Burst Lengths Supported (BL) 16 0Ch BL = 4, 8
Number of Banks on SDRAM Device 17 04h 4
CAS Latency (CL) 18 30h CL = 5, 4
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-1) 23 37h 3.70 ns (270.3 MHz)
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-2) 25 00h Not defined
Minimum Row Precharge Time (tRP) 27 32h 12.5 ns
5.0, CL = 5
3.37, CL = 4
Minimum Row Active to Row Active delay (tRRD) 28 1Eh 7.5 ns
3.0, CL = 5
2.03, CL = 4
Minimum RAS to CAS delay (tRCD) 29 32h 12.5 ns
5.0, CL = 5
3.37, CL = 4
Minimum Active to Precharge Time (tRAS) 30 2Dh 45.0 ns
18.0, CL = 5
12.16, CL = 4
Module Bank Density 31 80h 512 MB
Write recovery time (tWR) 36 3Ch 15.0 ns
6.0, CL = 5
4.05, CL = 4
Internal write to read command delay (tWTR) 37 1Eh 7.5 ns
3.0, CL = 5
2.03, CL = 4
Internal read to precharge command delay (tRTP) 38 1Eh 7.5 ns
3.0, CL = 5
2.03, CL = 4
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 41, 40 37h, 00h 55.0 ns
22.0, CL = 5
14.86, CL = 4
SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) 42, 40 4Bh, 00h 75.0 ns
30.0, CL = 5
20.27, CL = 4
Maximum device cycle time (tCKmax) 43 80h 8.0 ns
SPD Revision 62 12h Revision 1.2
Checksum for Bytes 0-62 63 98h 152 (true)
Manufacturer’s JEDEC ID Code 64-71 7Fh, 7Fh,
9Eh
Corsair
Module Part Number 73-90 CM2X1024-6400C3
Module Manufacturing Date 93-94 06h, 11h Year 2006, Week 17
Module Serial Number 95-98 00h, 00h,
00h, 00h
Not defined

Data of the "standard" SPD section are usual for Corsair modules. The fastest mode these modules are capable of is characterized by the cycle time of 2.5 ns (400 MHz, DDR2-800). This mode corresponds to the first supported tCL = 5, the full timings scheme is written as 5-5-5-18, which agrees with the official characteristics from the datasheet. Reduced CAS# latency (CL X-1 = 4) corresponds to the non-standard cycle time of 3.7 ns, that is approximately 270 MHz. It probably means DDR2-533 mode and the cycle time of 3.75 ns. Nevertheless, the incorrect cycle time results in fractional timings, which can be written (rounded to one figure after the dot) as 4-3.4-3.4-12.2. This scheme will most likely be rounded up by most BIOS's to 4-4-4-13. Nevertheless, DDR2-533 mode has grown outdated long ago for high-speed DDR2 modules, so these values hardly make sense — it would have been reasonable to remove them from SPD.

Manufacturer’s JEDEC ID Code and Part Number of the modules are correct. Interestingly, these modules also contain information about their manufacturing date (Week 17, 2006). Nevertheless, their serial number is still missing.

Let's review the most important data from the "non-standard" SPD section that corresponds to EPP profiles, represented by Bytes 99-127.

EPP Standard Description:

Parameter Byte(s)
(bits)
Value Expansion
EPP Identifier String 99-101 4E566Dh EPP SPD Support
EPP Profile Type Identifier 102 B1h Full Profiles
Profile for Optimal Performance 103 (1:0) 00h Profile 0
Enabled Profiles 103 (7:4) 03h Profile 0: available
Profile 1: available
Profile 0
Voltage Level 104 (6:0) 10h 2.2 V
Addr CMD rate 104 (7) 01h 2T
Cycle time (tCK) 109 25h 2.50 ns (200.0 MHz)
CAS# latency (tCL) 110 08h 3
Minimum RAS to CAS delay (tRCD) 111 28h 10.0 ns (4)
Minimum Row Precharge Time (tRP) 112 1Eh 7.5 ns (3)
Minimum Active to Precharge Time (tRAS) 113 16h 22.0 ns (12)
Write recovery time (tWR) 114 3Ch 15.0 ns (6)
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 115 37h 55.0 ns (22)
Profile 1
Voltage Level 116 (6:0) 10h 2.2 V
Addr CMD rate 116 (7) 01h 2T
Cycle time (tCK) 121 1Eh 1.875 ns (266.7 MHz)
CAS# latency (tCL) 122 20h 5
Minimum RAS to CAS delay (tRCD) 123 26h 9.5 ns (5.06)
Minimum Row Precharge Time (tRP) 124 26h 9.5 ns (5.06)
Minimum Active to Precharge Time (tRAS) 125 1Ch 28.0 ns (14.93)
Write recovery time (tWR) 126 3Ch 15.0 ns (8)
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 127 37h 55.0 ns (29.33)

You can see that our modules support the EPP standard and contain information on two full profiles (or four abbreviated profiles that lack most latency and voltage tweaks for various signal lines). The first profile (Profile 0) is considered to be optimal (recommended as a default profile). It corresponds to the 2.5ns cycle time (DDR2-800 mode). But unlike the standard SPD section, EPP Profile 0 for this mode specifies 3-4-3-8.8 timings (rounded up to 3-4-3-9), 2T address command rate and 2.2 V voltage, as well as other tweaks (timings and voltages), which are not published in the table. The second EPP profile (Profile 1) corresponds to DDR2-1066 mode with the 1.875ns cycle time. Corresponding timings are also fractional - 5-5.06-5.06-14.93. Motherboards with EPP support should detect this scheme as 5-5-5-15. Address command rate in this case is also 2T, voltage - 2.2 V.

Testbed configurations

Testbed 1

  • CPU: AMD Athlon 64 X2 4800+ (Socket AM2), 2.4 GHz (200 x12)
  • Chipset: NVIDIA nForce4 SLI X16, MCP590
  • Motherboard: ASUS CROSSHAIR, BIOS 0203 dated 09/12/2006
  • Memory: 2x1024 MB Corsair XMS2-6400C3 in DDR2-800 mode, 400 MHz (2400 /6), SLI-Ready Memory: "Disabled"

Testbed 2

  • CPU: AMD Athlon 64 X2 4800+ (Socket AM2), 2.4 GHz (200 x12)
  • Chipset: NVIDIA nForce4 SLI X16, MCP590
  • Motherboard: ASUS CROSSHAIR, BIOS 0203 dated 09/12/2006
  • Memory: 2x1024 MB Corsair XMS2-6400C3 in DDR2-800 mode, 400 MHz (2400 /6), SLI-Ready Memory: "Optimal" or "High Performance", SLI-OC: "Disabled"

Testbed 3

  • CPU: AMD Athlon 64 X2 4800+ (Socket AM2), 2.4 GHz (240 x10)
  • Chipset: NVIDIA nForce4 SLI X16, MCP590
  • Motherboard: ASUS CROSSHAIR, BIOS 0203 dated 09/12/2006
  • Memory: 2x1024 MB Corsair XMS2-6400C3 in DDR2-1066 mode, 480 MHz (2400 /5), SLI-Ready Memory: "High Frequency", SLI-OC: "Disabled"

Testbed 4

  • CPU: AMD Athlon 64 X2 4800+ (Socket AM2), 2.67 GHz (267 x10), 1.55 V
  • Chipset: NVIDIA nForce4 SLI X16, MCP590
  • Motherboard: ASUS CROSSHAIR, BIOS 0203 dated 09/12/2006
  • Memory: 2x1024 MB Corsair XMS2-6400C3 in DDR2-1066 mode, 536 MHz (2680 /5), SLI-Ready Memory: "High Frequency", SLI-OC: "Max"

Testbed 5

  • CPU: AMD Athlon 64 X2 4800+ (Socket AM2), 2.67 GHz (267 x10), 1.55 V
  • Chipset: NVIDIA nForce4 SLI X16, MCP590
  • Motherboard: ASUS CROSSHAIR, BIOS 0203 dated 09/12/2006
  • Memory: 2x1024 MB Corsair XMS2-6400C3 in DDR2-1066 mode, 575 MHz (2870 /5), SLI-Ready Memory: "High Frequency", SLI-OC: "Max"

Test Results

Performance tests

We ran our tests on the ASUS CROSSHAIR motherboard that supports EPP memory modules. EPP profiles can be enabled/disabled in BIOS Setup of this motherboard from the "SLI-Ready Memory" option, which can take the following values: "Disabled", "Optimal", "High Performance" and "High Frequency". "Disabled" corresponds to using standard SPD information to configure memory, "Optimal" corresponds to the optimal profile (according to EPP). The other values ("High Performance" and "High Frequency") correspond to maximum performance (minimal latencies at the standard frequency) and maximum memory frequency. "SLI-Ready Memory" is supplemented with the "SLI-OC" option to overclock a processor (from 0%, that is no overclocking, to 15% (MAX) at 1% steps) to get maximum memory performance. The motherboard manufacturer warns that this mode may require increasing the CPU voltage, which is only natural. Besides these options, the ASUS CROSSHAIR, like most other motherboards with EPP support, allows manual configuration of lots of various timing parameters, supported by the new DDR2 controller in AM2 processors, and various tweaks of latencies and voltages, provided by the new EPP standard. Most of these parameters were set by default in our tests ("Auto"), that is we completely trusted automatic optimization of memory characteristics by EPP profiles.

We used five tests of these modules (Testbeds 1 — 5):

1. SLI-Ready Memory: Disabled - default SPD mode, that is DDR2-800 with 5-5-5-18 timings (2T address command rate, selected by the motherboard)

2. SLI-Ready Memory: "High Performance" or "Optimal" - DDR2-800 mode, 3-4-3-9-2T latencies, that is EPP Profile 0 (optimal)

3. SLI-Ready Memory: "High Frequency". The motherboard operating in this mode reconfigured FSB clock and CPU multiplier so that its clock frequency remained on the previous level (2400 MHz = 240 MHz x10), but the memory frequency was increased from 400 MHz to 480 MHz (2400 /5). Memory timings in this case were also selected according to EPP Profile 1 — 5-5-5-15-2T.

4. SLI-Ready Memory: "High Frequency". This test mode is similar to the previous one, but we allowed the motherboard to overclock the processor by setting "SLI-OC" to "MAX" (it overclocks the CPU by no more than 15%). We also increased the CPU voltage to 1.45 V, to make sure it worked well at the increased frequency. The latter was 2680 MHz (268 MHz x10). This very frequency is sufficient for the memory bus to reach 533 MHz, even a tad higher (2680 MHz /5 = 536 MHz). It's easy to calculate that the CPU is overclocked by approximately 11.7%.

5. SLI-Ready Memory: "High Frequency", SLI-OC: "MAX". We intended to get maximum memory frequency in the last test mode by overclocking the CPU manually (increasing the master clock rate). We determined the latter experimentally (when there disappeared errors in memory stability test), it was set to 287 MHz (2870 MHz CPU, 1.5V at the core), which corresponds to the memory frequency of 575 MHz. Memory voltage was raised to the maximum reasonable value of 2.4V, timings remained the same — 5-5-5-15-2T.

Our memory test procedure has been supplemented with readings of average and maximum real memory bandwidth in case of parallel memory access from both cores. It's done with RightMark Multi-Threaded Memory Test, included into the latest RightMark Memory Analyzer 3.72. It has to do with the fact that the current generation of dual-core processors from AMD does not reveal the full potential of high-speed DDR2 memory in dual-channel mode, as we demonstrated here. We have recently proved that the dual-channel memory access mode lifts some limitations that have to do with microarchitectural peculiarities of the CPU core. Thus, it allows to reach higher real memory bandwidths and reveals real characteristics of the memory system.

Parameter Testbed 1 Testbed 2 Testbed 3 Testbed 4 Testbed 5
Timings
5-5-5-18-2T
3-4-3-9-2T
5-5-5-15-2T
5-5-5-15-2T
5-5-5-15-2T
Average memory read bandwidth, GB/sec
(1 core)
3.95
4.12
4.18
4.63
4.96
Average memory write bandwidth, GB/sec
(1 core)
3.24
3.40
3.47
3.85
4.06
Max. memory read bandwidth, GB/sec
(1 core)
7.83
8.09
8.07
8.99
9.58
Max. memory write bandwidth, GB/sec
(1 core)
6.92
6.89
6.90
7.71
8.00
Average memory read bandwidth, GB/sec
(2 cores)
6.60
7.00
7.13
7.91
8.57
Average memory write bandwidth, GB/sec
(2 cores)
3.95
4.27
4.38
5.06
5.24
Max. memory read bandwidth, GB/sec
(2 cores)
8.51
9.28
9.66
10.69
11.84
Max. memory write bandwidth, GB/sec
(2 cores)
6.47
6.64
6.62
7.39
7.93
Minimum pseudo-random access latency, ns
28.0
25.6
25.4
23.0
21.6
Minimum random access latency*, ns
80.7
75.6
74.3
65.9
64.3

*32 MB block size

The worst results (relatively low memory bandwidth values and high latencies) are expectedly demonstrated in the first test mode, standard DDR2-800 with 5-5-5-18 timings. The optimal EPP mode (Profile 0) and the extreme timings scheme (3-4-3-9) for DDR2-800 (Mode 2) have a noticeable effect on memory bandwidth (in the best case - maximum real bandwidth of memory read by both cores simultaneously - it grows from 8.51 GB/sec to 9.28 GB/sec) and memory access latencies (they go down from 80.7ns to 75.6ns in the worst case).

Higher memory frequency (480 MHz) at the same CPU clock rate of 2.4 GHz (Mode 3) slightly reduces latencies and has an insignificant effect on memory bandwidth (its peak value grows from 9.28 GB/sec to 9.66 GB/sec). Memory bandwidth and latencies can be improved only by overclocking a processor. In case of the native DDR2-1066 mode for this modules (EPP Profile 1, Mode 4), maximum real bandwidth of memory read by two cores grows to 10.69 GB/sec, maximum latencies of random memory access are reduced to 65.9ns. Overclocking memory modules to the maximum possible frequency of 575 MHz ("DDR2-1150", Mode 5) contributes to a further increase in maximum real memory bandwidth to 11.84 GB/sec and some reduction of latencies. Interestingly, upgrading from DDR2-1066 to "DDR2-1150" gains 10.8% of maximum real memory bandwidth, while the relative increase in memory frequency (from 533 MHz to 575 MHz) is just 7.8%. That's another proof that the system bottleneck in this case is not memory itself (the imposing theoretical peak memory bandwidth in "DDR2-1150" mode is 18.4 GB/sec), but the DDR2 controller integrated into AMD Athlon 64 X2. Its frequency must be as high as possible to reveal its full potential.

Stability tests

Timing values, except for tCL and address command rate, were adjusted "on the fly" with the built-in RMMA feature that allows to change dynamically memory settings supported by the chipset. Memory operating stability was evaluated with an auxiliary utility RightMark Memory Stability Test, included into RMMA.

Parameter Testbed 1 Testbed 2 Testbed 3 Testbed 4 Testbed 5
Timings
4-4-3-2T
3-4-3-2T
4-4-4-2T
5-5-4-2T
5-5-5-2T
Average memory read bandwidth, GB/sec
(1 core)
4.00
4.12
4.28
4.62
4.96
Average memory write bandwidth, GB/sec
(1 core)
3.35
3.40
3.09
3.32
4.06
Max. memory read bandwidth, GB/sec
(1 core)
7.94
8.09
8.19
8.98
9.58
Max. memory write bandwidth, GB/sec
(1 core)
6.93
6.89
6.92
7.72
8.00
Average memory read bandwidth, GB/sec
(2 cores)
6.90
7.00
7.46
8.04
8.57
Average memory write bandwidth, GB/sec
(2 cores)
4.17
4.27
4.76
4.69
5.24
Max. memory read bandwidth, GB/sec
(2 cores)
9.27
9.28
10.58
10.77
11.84
Max. memory write bandwidth, GB/sec
(2 cores)
6.61
6.64
6.74
7.43
7.93
Minimum pseudo-random access latency, ns
27.3
25.6
24.2
23.1
21.6
Minimum random access latency*, ns
77.1
75.6
73.6
68.0
64.3

*32 MB block size

We shall not go into details, because our readings look quite natural. In some cases (Modes 2 and 5) they copy the results published above. In return, we shall pay attention to minimal timings obtainable in this or that case.

So, we managed to get only 4-4-3-2T timings in the first mode (DDR2-800 without using EPP) even with the memory voltage increased to 2.2V. Note that our modules actually allowed 4-4-3-1T or 4-3-3-2T timings in this mode — these timings did not result in immediate system freezes, but there still appeared errors in both cases sooner or later. We did not expect this result, considering that the timings were much lower even in the standard Test Mode 2 using EPP data (3-4-3-9-2T). One thing is clear: such extreme overclocking of timings requires data from the corresponding EPP profile that help tweak memory parameters (timings and voltages). As these parameters can be adjusted usually only by motherboards with EPP support, this feature becomes important to make these memory modules work in this mode. Thus, a "usual" motherboard may fail to support these modules with recommended settings that are guaranteed to work.

What concerns the optimal EPP mode (DDR2-800), no miracles here — timings remained on the level of 3-4-3-2T (as usual, changing tRAS has no effect on memory stability, so this parameter is not included into timing schemes, published here). To be more exact, memory modules allowed to set timings to 3-3-3-2T in this case, but it resulted in some errors.

The most noticeable overclocking of timings is demonstrated in the third case, when the CPU clock rate remains nominal (2.4 GHz), but memory frequency grows to 480 MHz. As 5-5-5-15-2T timings, written in EPP for this case, are intended for the DDR2-1066 mode, they can be reduced to 4-4-4-2T, if the frequency is reduced. Moreover, these memory modules can be stable even with 4-4-3-2T timings. But in our case this timings scheme resulted in errors.

We also managed to reduce timings, when the CPU was overclocked to 2.68 GHz, sufficient for 533 MHz memory. In this mode we managed to set timings to 5-5-4-2T without losing operating stability. But when we reduced them to 5-4-4-2T, there appeared errors.

Bottom line

Corsair XMS2-6400C3 memory modules are high-end high-speed modules that can operate not only in the official DDR2-800 mode (these modules are designed for it) with 3-4-3-9-2T timings, but also in the fastest unofficial DDR2-1066 mode. Moreover, these modules can reach a higher operating frequency. In our case it was approximately 575 MHz ("DDR2-1150") at 2.4V and 5-5-5-15-2T timings.

These modules, which SPD chips contain data of the new open EPP standard, are fully compatible with the ASUS CROSSHAIR motherboard supporting this standard.

What concerns the overclocking potential of these modules in timings, they were stable in DDR2-800 mode with the recommended 3-4-3-2T timings. But EPP support in your motherboard plays an important role in providing stability. If your motherboard does not use EPP data, these memory modules can operate in DDR2-800 mode at 2.2V only with 4-4-4-2T timings. What concerns the fastest DDR2-1066 mode, our modules worked with 5-5-4-2T timings - this scheme is a tad lower than the recommended 5-5-5-15-2T timings. The modules under review are no worse in this parameter than the previously reviewed Corsair XMS2-8500C5 modules (they also support EPP), and they are even better in DDR2-800 mode.


Dmitri Besedin (dmitri_b@ixbt.com)
November 27, 2006

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