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Memory Module Analysis. Part 23: Corsair DDR2-1066 Modules with EPP Support (XMS2-8500C5)

August 21, 2006




We proceed with the analysis of the most important characteristics of high-performance DDR2 memory modules using our RightMark Memory Analyzer. Today we are going to review the first memory modules of the high-speed unofficial category DDR2-1066 from Corsair that support SPD EPP (Enhanced Performance Profiles), designed by Corsair and NVIDIA — 2GB dual-channel kit XMS2-8500C5 for the AMD AM2 platform.

Manufacturer Information

Module manufacturer: Corsair Memory
Manufacturer of module chips: unknown
Web site of the module manufacturer: http://www.corsairmemory.com/corsair/xms2.html

Module Exterior

Photo of the memory module




Module Part Number

Module Part Number Expansion




The manufacturer's web site does not publish the DDR2 Part Number expansion of XMS2-series memory modules. TWIN2X1024-8500 Specs run that this product is a kit of two 1 GB modules, based on sixteen 64M x8 chips. These modules support the open standard EPP (SPD extension), developed by Corsair and NVIDIA. It allows to configure memory modules for maximum performance automatically on motherboards that support this standard. The manufacturer guarantees operation of these modules in DDR2-1066 mode with EPP 5-5-5-15-2T timings and 2.2 V voltage. But the default mode in the standard SPD section is the maximal standard DDR2-800 mode with 5-5-5-15 timings.

SPD chip data

Description of the general SPD standard:

Description of the specific SPD standard for DDR2:

Parameter Byte Value Expansion
Fundamental Memory Type 2 08h DDR2 SDRAM
Number of Row Addresses on this assembly 3 0Eh 14 (RA0-RA13)
Number of Column Addresses on this assembly 4 0Ah 10 (CA0-CA9)
Number of DIMM Banks 5 61h 2 physical banks
Data Width of this assembly 6 40h 64 bit
Voltage Interface Level of this assembly 8 05h SSTL 1.8V
SDRAM Cycle time (tCK) at maximum supported CAS# latency (CL X) 9 25h 2.50 ns (400.0 MHz)
DIMM configuration type 11 00h Non-ECC
Refresh Rate/Type 12 82h 7.8125 ms — 0.5x reduced self-refresh
Primary SDRAM Width (organization type) of the memory module chips 13 08h x8
Error Checking SDRAM Width (organization type) of the memory chips in the ECC module 14 00h Not defined
Burst Lengths Supported (BL) 16 0Ch BL = 4, 8
Number of Banks on SDRAM Device 17 04h 4
CAS Latency (CL) 18 30h CL = 5, 4
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-1) 23 37h 3.70 ns (270.3 MHz)
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-2) 25 00h Not defined
Minimum Row Precharge Time (tRP) 27 32h 12.5 ns
5.0, CL = 5
3.37, CL = 4
Minimum Row Active to Row Active delay (tRRD) 28 1Eh 7.5 ns
3.0, CL = 5
2.03, CL = 4
Minimum RAS to CAS delay (tRCD) 29 32h 12.5 ns
5.0, CL = 5
3.37, CL = 4
Minimum Active to Precharge Time (tRAS) 30 2Dh 45.0 ns
18.0, CL = 5
12.16, CL = 4
Module Bank Density 31 80h 512 MB
Write recovery time (tWR) 36 3Ch 15.0 ns
6.0, CL = 5
4.05, CL = 4
Internal write to read command delay (tWTR) 37 1Eh 7.5 ns
3.0, CL = 5
2.03, CL = 4
Internal read to precharge command delay (tRTP) 38 1Eh 7.5 ns
3.0, CL = 5
2.03, CL = 4
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 41, 40 37h, 00h 55.0 ns
22.0, CL = 5
14.86, CL = 4
SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) 42, 40 4Bh, 00h 75.0 ns
30.0, CL = 5
20.27, CL = 4
Maximum device cycle time (tCKmax) 43 80h 8.0 ns
SPD Revision 62 12h Revision 1.2
Checksum for Bytes 0-62 63 98h 152 (true)
Manufacturer’s JEDEC ID Code 64-71 7Fh, 7Fh,
9Eh
Corsair
Module Part Number 73-90 CM2X1024-8500
Module Manufacturing Date 93-94 00h, 00h Not defined
Module Serial Number 95-98 00h, 00h,
00h, 00h
Not defined

Data of the "standard" SPD section are usual for Corsair modules. The fastest mode these modules are capable of is characterized by the cycle time of 2.5 ns (400 MHz, DDR2-800). This mode corresponds to the first supported value of tCL = 5, the full timing scheme is written as 5-5-5-18, which slightly disagrees with official characteristics, published in the datasheet on these modules (DDR2-800, 5-5-5-15). Reduced CAS# latency (CL X-1 = 4) corresponds to the non-standard cycle time of 3.7 ns, 270 MHz — it probably means DDR2-533 and the cycle time of 3.75 ns. Nevertheless, the incorrect cycle time results in fractional timings, which can be written (rounded to one figure after the dot) as 4-3.4-3.4-12.2, which will most likely be rounded up by most BIOS's to 4-4-4-13. In fact, DDR2-533 mode is evidently irrelevant for such fast modules, so these values hardly make any sense — it would have been better to remove them from SPD.

Manufacturer’s JEDEC ID Code and Part Number of the module are correct. Nevertheless, as in the other Corsair modules, the SPD chip of these modules lacks information about the manufacturing date and serial number.

Well, let's review the most important data from the "non-standard" SPD section that corresponds to EPP profiles, represented by Bytes 99-127.

EPP Standard Description:

Parameter Byte(s)
(bits)
Value Expansion
EPP Identifier String 99-101 4E566Dh EPP SPD Support
EPP Profile Type Identifier 102 B1h Full Profiles
Profile for Optimal Performance 103 (1:0) 01h Profile 1
Enabled Profiles 103 (7:4) 03h Profile 0: available
Profile 1: available
Profile 0
Voltage Level 104 (6:0) 08h 2.0 V
Addr CMD rate 104 (7) 01h 2T
Cycle time (tCK) 109 25h 2.50 ns (200.0 MHz)
CAS# latency (tCL) 110 10h 4
Minimum RAS to CAS delay (tRCD) 111 28h 10.0 ns (4)
Minimum Row Precharge Time (tRP) 112 28h 10.0 ns (4)
Minimum Active to Precharge Time (tRAS) 113 1Eh 30.0 ns (12)
Write recovery time (tWR) 114 3Ch 15.0 ns (6)
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 115 37h 55.0 ns (22)
Profile 1
Voltage Level 116 (6:0) 10h 2.2 V
Addr CMD rate 117 (7) 01h 2T
Cycle time (tCK) 121 1Eh 1.875 ns (266.7 MHz)
CAS# latency (tCL) 122 20h 5
Minimum RAS to CAS delay (tRCD) 123 26h 9.5 ns (5.06)
Minimum Row Precharge Time (tRP) 124 26h 9.5 ns (5.06)
Minimum Active to Precharge Time (tRAS) 125 1Ch 28.0 ns (14.93)
Write recovery time (tWR) 126 3Ch 15.0 ns (8)
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 127 37h 55.0 ns (29.33)

You can see that our modules support the EPP standard and contain information on two full profiles (or four abbreviated profiles that lack most latency and voltage tweaks for various signal lines). The first profile (Profile 0) corresponds to the 2.5ns cycle time, that is DDR2-800 mode. But unlike the standard SPD section, EPP Profile 0 specifies 4-4-4-12 for this mode, 2T address command rate and 2.0 V voltage, as well as other timing and voltage parameters that are not included into the table. The second EPP profile (Profile 1) is marked as optimal (recommended to be used by default), it corresponds to DDR2-1066 mode with the 1.875ns cycle time. Corresponding timings cannot be represented by integer values. It's written as 5-5.06-5.06-14.93, which must be read by motherboards with EPP support as 5-5-5-15. Address command rate in this case is also 2T, but the voltage is increased to 2.2 V.

Testbed configurations

Testbed 1

  • CPU: AMD Athlon 64 X2 4800+ (Socket AM2), 2.4 GHz (200 x12)
  • Chipset: NVIDIA nForce4 SLI X16, MCP590
  • Motherboard: ASUS M2N32-SLI Deluxe, BIOS 0603 dated 06/27/2006
  • Memory: 2x1024 MB Corsair XMS2-8500C5 in DDR2-800 mode, 400 MHz (2400 /6), SLI-Ready Memory: "Disabled"

Testbed 2

  • CPU: AMD Athlon 64 X2 4800+ (Socket AM2), 2.4 GHz (200 x12)
  • Chipset: NVIDIA nForce4 SLI X16, MCP590
  • Motherboard: ASUS M2N32-SLI Deluxe, BIOS 0603 dated 06/27/2006
  • Memory: 2x1024 MB Corsair XMS2-8500C5 in DDR2-800 mode, 400 MHz (2400 /6), SLI-Ready Memory: "High Performance"

Testbed 3

  • CPU: AMD Athlon 64 X2 4800+ (Socket AM2), 2.4 GHz (240 x10)
  • Chipset: NVIDIA nForce4 SLI X16, MCP590
  • Motherboard: ASUS M2N32-SLI Deluxe, BIOS 0603 dated 06/27/2006
  • Memory: 2x1024 MB Corsair XMS2-8500C5 in DDR2-1066 mode, 480 MHz (2400 /5), SLI-Ready Memory: "Optimal" or "High Frequency", SLI-OC: "Disabled".

Testbed 4

  • CPU: AMD Athlon 64 X2 4800+ (Socket AM2), 2.67 GHz (267 x10), 1.55 V
  • Chipset: NVIDIA nForce4 SLI X16, MCP590
  • Motherboard: ASUS M2N32-SLI Deluxe, BIOS 0603 dated 06/27/2006
  • Memory: 2x1024 MB Corsair XMS2-8500C5 in DDR2-1066 mode, 533 MHz (2670 /5), SLI-Ready Memory: "Optimal" or "High Frequency", SLI-OC: "Max"

Test Results

Performance tests

We ran our tests on the ASUS M2N32-SLI Deluxe motherboard that supports EPP memory modules. EPP profiles can be enabled/disabled in BIOS Setup of this motherboard from the "SLI-Ready Memory" option, which can take the following values: "Disabled", "Optimal", "High Performance" and "High Frequency". "Disabled" evidently means using the standard memory settings from SPD. There are also "Optimal" (according to EPP data), "High Performance" and "High Frequency" profiles (these notions are rather wide, so the choice of a profile probably depends on your memory modules). In addition to the "SLI-Ready Memory" option we have "SLI-OC". It allows to overclock a processor by specified percent (from 0%, that is no overclocking, to 14% at 1% steps, plus the "MAX" option, which seems to correspond to 15% overclocking) to get maximum memory performance. The motherboard manufacturer warns that this mode may require increasing the CPU voltage, which is only natural. Along with these options, the ASUS M2N32-SLI Deluxe motherboard offers a great number of timing settings supported by the new DDR2 controller in AM2 processors (from standard tCL, tRCD, tRP, and tRAS to such insignificant settings as tRDRD/tWRWR), as well as various tweaks of latencies and voltages provided by the new EPP standard. Most of these parameters were set by default in our tests ("Auto"), that is we completely trusted automatic optimization of memory characteristics by EPP profiles.

We tested these modules in four different ways:

1. SLI-Ready Memory: Disabled, it corresponds to the default SPD mode, that is DDR2-800, 5-5-5-18 timings, 2T address command rate

2. SLI-Ready Memory in "High Performance" mode, which also corresponds to DDR2-800, but with 4-4-4-12-2T latencies, EPP Profile 0.

3. SLI-Ready Memory in "Optimal" or "High Frequency" modes. It makes no difference in case of our modules, as the optimal EPP profile is set to Profile 1, which corresponds to maximum frequency. Interestingly, the motherboard operating in this mode reconfigured FSB clock and CPU multiplier so that its clock frequency remained on the previous level (2400 MHz = 240 MHz x10), but the memory frequency was increased from 400 MHz to 480 MHz (2400 /5). Timings are selected by Profile 1 — 5-5-5-15-2T.

4. The last test mode is similar to the previous one, but we allowed the motherboard to overclock the processor by setting "SLI-OC" to "MAX" (as we have already noted, it probably overclocks CPU by no more than 15%). We also increased the CPU voltage to 1.55 V, to make sure it worked well at the increased frequency. It ran at 2670 MHz (267 MHz x10) — this frequency is sufficient to raise the memory bus clock to approximately 533 MHz (2670 /5). Thus, the processor was overclocked by approximately 11%.

Parameter Testbed 1 Testbed 2 Testbed 3 Testbed 4
Timings
5-5-5-18-2T
4-4-4-12-2T
5-5-5-15-2T
5-5-5-15-2T
Average memory read bandwidth, MB/sec
3934
4051
4178
4668
Average memory write bandwidth, MB/sec
3284
3383
3488
3891
Max. memory read bandwidth, MB/sec
7813
7976
8081
9041
Max. memory write bandwidth, MB/sec
6927
6938
6899
7711
Minimum pseudo-random access latency, ns
28.1
26.7
25.4
22.7
Maximum pseudo-random access latency, ns
31.0
29.5
28.4
25.4
Minimum random access latency*, ns
80.3
76.6
73.9
66.4
Maximum random access latency*, ns
85.4
82.8
76.2
68.3

*32 MB block size

Test results in all the four modes are quite obvious. Differences between the first two modes, which differ only in timings, are less noticeable. Maximum real memory bandwidth is about 7.8-7.9 GB, which conforms well with the fact that even DDR2-800 memory (in dual-channel mode) is evidently excessive for single-core memory access from AMD AM2 processors. In conformity with this fact, memory bandwidth values demonstrated in the third mode (480 MHz memory, DDR2-960) are practically no different from the results demonstrated in the first two cases. Higher memory frequencies, while the CPU clock is preserved at 2.4 GHz, slightly reduce latencies, which is especially noticeable during random memory access. Only in the last case (Testbed 4), when we overclock the processor to 2.67 GHz (by 11%), maximum real memory bandwidth grows to about 9.0 GB/s, that is approximately by the same 11%. At the same time, we can see some latency reduction that has to do with lower absolute timings (5-5-5-15 at 533 MHz — lower than the same timing scheme at 480 MHz).

Stability tests

Memory timings, except for tCL, were adjusted "on the fly" with the built-in RMMA feature that allows to change dynamically memory settings, supported by the chipset (we used an intermediate version of this utility, RMMA 3.7, that already supports DD2 memory controller in AM2 processors.) Memory operating stability was evaluated with an auxiliary utility RightMark Memory Stability Test, included into RMMA.

Parameter Testbed 1 Testbed 2 Testbed 3 Testbed 4
Timings
4-4-3-1T
(2.0 V)
4-4-3-1T
(2.0 V)
5-4-3-2T
(2.2 V)
5-5-4-2T
(2.2 V)
Average memory read bandwidth, MB/sec
4171
4174
4170
4664
Average memory write bandwidth, MB/sec
3429
3456
3335
3740
Max. memory read bandwidth, MB/sec
8128
8154
8109
9012
Max. memory write bandwidth, MB/sec
6846
6854
6916
7723
Minimum pseudo-random access latency, ns
25.3
25.2
25.4
22.8
Maximum pseudo-random access latency, ns
28.1
28.1
28.5
25.5
Minimum random access latency*, ns
77.9
77.5
74.8
66.0
Maximum random access latency*, ns
80.5
79.6
76.8
67.9

*32 MB block size

Memory voltage in the first case was specified manually in compliance with the official recommendations, written in EPP profiles (2.0 V for DDR2-800). In all the other cases we left it up to the motherboard, which could configure system components automatically by EPP data. Minimal timings in the first two cases with 400 MHz memory were 4-4-3 at the reduced address command rate 1T (as always, tRAS values were not included into this scheme, as it could take any value, up to 5, without any effect on memory stability). These timings expectedly reduced latencies (compared to standard 4-4-4-12 and, especially, 5-5-5-18), but had practically no effect on memory bandwidth.

In the third case, minimal stable timings for 480 MHz memory were 5-4-3 at the address command rate of 2T. Memory frequency increased to 533 MHz (Testbed 4) actually allowed to use the same timings, but errors occurred rather quickly. So the minimum possible timings in the native DDR2-1066 mode are 5-5-4 and the 2T address command rate. Nevertheless, "overclocking timings" had practically no effect on memory bandwidth (as in the first two cases) as well as on memory access latencies.

Bottom line

Corsair XMS2-8500C5 proved to be high-performance high-end modules, which can operate in the official DDR2-800 mode as well as in the unofficial fastest DDR2-1066 mode (at the moderately high voltage of 2.2V). These modules, which SPD chips contain data of the new open EPP standard, are fully compatible with the ASUS M2N32-SLI Deluxe motherboard supporting this standard. Like the previously reviewed Corsair XMS2-8500, these modules offer moderate timing overclocking potential (compared to earlier top solutions from Corsair) — in the official DDR2-800 mode they can operate with 4-4-3-1T timings (2.0 V), the fastest DDR2-1066 mode requires increasing this scheme to 5-5-4-2T, still a tad lower than the recommended 5-5-5-2T scheme.


Dmitri Besedin (dmitri_b@ixbt.com)
August 18, 2006.



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