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VIA Nano CPUID Tricks



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Let's see some ID

First of all, let's say a few words about CPUID. This is a processor command that returns processor's "passport." It was first introduced in higher-end 486 and Pentium processors. Its presence is marked by the possibility to overwrite the 21st bit of the flag register. The command has an implicit argument (the passport page in the EAX register) and it returns 16B in the registers EAX, EBX, ECX and EDX. This is what a program needs to determine features and capabilities of a processor. However, there may be exceptions in real life. Below is Nano's table of returned values.


Page (EAX) EAX EBX ECX EDX
1st part
CPU name Max. page number in the 1st part Vendor string (EBX-EDX-ECX, see table below)
00 00 00 00 00 00 00 0A 75 6E 65 47 6C 65 74 6E 49 65 6E 69
10 'Cent' 'auls' 'aurH'
Main functions and commands Family; model; stepping Brand; cache line flush size; logical cores no.; 1st APIC controller number Function flags
00 00 00 01 00 00 06 F2 00 01 08 00 00 00 63 A9 AF C9 FB FF
6; F; 2 No; 64B; 1; 0 Almost everything what a modern CPU has
Cache and TLB descriptors (bytewise) 15 descriptors (except for AL that stands for the number of requests of this page to get all descriptors)
00 00 00 02 02 B3 B0 01 (←AL) 00 00 00 00 00 00 00 00 2C 04 30 7D
1 request; TLB-I for 4MB pages: 2 entries, 2 ways; TLB-I/-D for 4KB pages: 128 entries, 4 ways each Zero descriptors L2: 2MB, 8 ways, 64 B/page; TLB-D for 4MB pages: 8 entries, 4 ways; L1D and L1I: 32KB, 8 ways, 64 B/page each
CPU serial number (if present)
00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Cache parameters (due to an error in WinNT only available if the MISC_ENABLE.LCMV bit is set to 0 in the MSR 1A0 register)
00 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Debug monitor parameters Min. monitor string size Max. monitor string size Treat interrupts as halts; MWAIT events enumerating Number of power-saving C-substates for MWAIT
00 00 00 05 00 00 00 40 00 00 00 40 00 00 00 03 00 02 22 20
64B 64B Yes; Yes 0 for C0, 2 for C1-C4
Power management parameters (with MISC_ENABLE.LCMV=0)
00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Reserve
00 00 00 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Direct Cache Access parameters
00 00 00 09 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Performance counters parameters Revision; number and capacity of counters; vector length in EBX Unavailability parameters Reserve Number and capacity of fixed counters
00 00 00 0A 06 28 03 02 00 00 00 00 00 00 00 00 00 00 05 03
2; 3; 40; 6 All events available   3; 40
2nd part
Additional name Max. page number in the 2nd part Manufacturer name (for AMD and Transmeta)
80 00 00 00 80 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00
8 Empty
Additional parameters Family, model, stepping Package and brand (for AMD) Function flags
80 00 00 01 00 00 00 00 00 00 00 00 00 00 00 01 2A 10 08 00
No additions Empty Additional flags
Full processor name (sometimes programmed via MSR)
80 00 00 02 20 20 20 20 20 20 20 20 20 20 20 20 56 20 20 20
4 spaces 4 spaces 4 spaces 3 spaces, 'V'
80 00 00 03 4E 20 41 49 20 6F 6E 61 63 6F 72 70 6F 73 73 65
'IA N' 'ano ' 'proc' 'esso'
80 00 00 04 32 4C 20 72 40 30 30 32 30 30 36 31 00 7A 48 4D
'r L2' '200@' '1600' 'MHz'
L1 and primary TLB parameters 4MB TLB for data and code (number of ways and size) 4KB TLB for data and code (number of ways and size) L1D: size; number of ways and lines per tag; line size L1I: size; number of ways and lines per tag; line size
80 00 00 05 00 00 00 00 08 80 08 80 40 10 01 40 40 10 01 40
No such TLB 128 entries and 8 ways each 64KB; 16; 1; 64B 64KB; 16; 1; 64B
L2, L3, TLB L2 parameters 4MB TLB L2 for data and code (number of ways and size) 4KB TLB L2 for data and code (number of ways and size) L2: size; number of ways and lines per tag; line size L3: size; number of ways and lines per tag; line size
80 00 00 06 00 00 00 00 00 00 00 00 04 00 81 40 00 00 00 00
No such TLB No such TLB 1MB; 16; 1; 64B No L3
Advanced power management parameters
80 00 00 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Miscellaneous parameters Virtual and physical addressing capacity ? Number of cores; core number capacity in APIC ?
80 00 00 08 00 00 30 24 00 00 00 00 00 00 00 00 00 00 00 00
48; 36 ? 1; 0 ?

Name string Manufacturer
AuthenticAMD AMD
CentaurHauls Centaur (IDT, VIA)
CyrixInstead Cyrix
Genuine  RDC RDC
GenuineIntel Intel
GenuineTMx86 Transmeta
Geode by NSC National Semiconductor
NexGenDriven NexGen
RiseRiseRise Rise Technology
SiS SiS SiS SiS
UMC UMC UMC UMC
Vortex86 SoC Vortex

VIA processors also have the 3rd part, starting from the page C0'00'00'00. It describes specific functions (e.g. PadLock instructions) and contains the original "Family, model, stepping" string. In our tests we changed vendor name to "GenuineIntel," and its place in the hierarchy to "6; 17; 0" (EAX=00'01'06'70), even though stepping 0 means it's an engineering sample not intended for sale (which is indicated by the letters "ES" on the second screenshot).

As you can see, not all the supplied information is correct, even if no strings have been changed. Cache and TLB parameters used to be provided by descriptors on page 2 of the 1st part. But one byte is not enough for all possible combinations, that's why caches and TLB are described thoroughly in the 2nd part, and this is the place to search for programs like CPU-Z. For examples, there's no descriptor "L1D: 64KB, 2 ways and 64 line" (like that of modern AMD chips), but all applications show the correct cache parameters for such processors. However, the CPU-Z screenshot shows that this isn't so for VIA Nano (and for all CPUs most likely). It seems that CPU-Z doesn't actually read cache parameters with CPUID, but just obtains those from its database, based on the vendor name and the "Family, model, stepping" string. It's the same substitution as that of Intel dispatchers.

Of course, some manufacturers just don't care to accurately specify parameters of their CPUs. For example, the first AMD Duron processors reported about having 1KB L2. So in order to provide correct data on even the first processor modifications, applications just keep the "correct values" stored in their tables. When a truly unknown CPU is involved, there's sense in reading the data directly by means of CPUID. Otherwise one may try to fool both applications and users. As for Intel, the company openly states in its documentation that if vendor string isn't "GenuineIntel," one shouldn't rely upon the interpretation of other fields the documentation provides, including the list of supported instruction sets. However all other processor manufacturers are encoding CPUID passports in exactly the same way, with the same pages, fields and interpretations.


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