In the previous article devoted to benchmarking an engineering sample of a quad-core AMD Phenom we failed to "cross all t's," because this processor has a bug officially acknowledged by AMD. Thus, we could benchmark Phenom either in a reduced performance mode (with patched BIOS, which disables some processor units) or without the patch, which potentially allowed mistakes in their operation. Our testbed did not freeze even once, and the patchless mode theoretically shows the real performance of future "debugged" processors, but our article still produced an impression of being incomplete. And now we have an AMD Phenom X4 9850, B3 stepping. This bug is fixed here. The processor operates at 2.5 GHz, it possesses an improved integrated Northbridge (2 GHz), and it even supports DDR2-1066. To all appearances, it's indeed the fastest solution AMD can offer now, so it will be interesting to compare Phenom X4 9850 with Intel processors. We've selected four dual- and quad-core processors from Intel based on the Core 2 architecture, operating at about 2.5 GHz, with new and old cores. So Phenom will be surrounded by possible direct competitors, which should help us analyze its performance in a proper way.

If you are interested in technical details about the architecture of the new processor from AMD and its notorious bug, you can read our previous articles - Detailed Platform Analysis in RightMark Memory Analyzer. Part 15: AMD Phenom X4 and Bug in AMD Phenom X4 Processors. Effect of AMD's Patch on Low-Level Characteristics of Processor and Platform. Here we'll just publish a brief list of peculiarities of the Phenom (K10) architecture versus the previous architecture from AMD (Athlon 64 X2 / K8).

• 128-bit (versus 64-bit in AMD K8) floating point (FP) execution units
• L1-LSU (Load-Store Unit) bus is expanded to 2x128 bit (read) and 2x64 bit (write)
• L1-L2 cache bus in the processor core is expanded to 128 bit
• Data prefetch into L1 cache
• Shared L3 instruction/data cache of exclusive (non-inclusive) architecture in the integrated memory controller
• Integrated dual-channel memory controller (2x64 bit, support for ganged or unganged modes) for DDR2 and DDR3 memory (only DDR2 in the first processors)
• Improved branch prediction unit, which can now predict indirect branches
• Sideband Stack Optimizer, a part of the decoder (similar to Stack Pointer Tracker in the Intel Core architecture)
• Significantly improved (faster) execution of SSE commands

Well, it all sounds great. And now let's see how well it works in practice...

Hardware and Software

Testbed configurations

• Memory: 4 GB (4 x 1 GB modules)
• HDD: Samsung HD401LJ (SATA-2)
• Coolers: Thermaltake TMG i1, Thermaltake TMG A1
• Power supply unit: Cooler Master RS-A00-EMBA

* Per single core in multi-core processors
** "X x Y" means "X KB per each of Y cores"
*** In AMD processors it's memory controller bus frequency
**** Specified differently in Intel and AMD processors, so a direct comparison would be incorrect

Software

* Means that two or more simultaneously active threads are actually present during tests; not just the fact that a process generates several threads.

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