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Memory Module Analysis. Part 9: Samsung DDR2-667

March 30, 2005



We proceed with the series of articles devoted to the low level analysis of the most important characteristics of DDR2 memory modules using our RightMark Memory Analyzer universal test package. This article will review two Samsung DDR2-667 memory module types, represented by 256 MB and 512 MB sample pairs.

Manufacturer Information

Module and chip manufacturer: Samsung Semiconductor
Web site of the module and chip manufacturer:
http://www.samsung.com/Products/Semiconductor/DRAM/DDR2SDRAM/index.htm

Module Appearance

Photo of the memory modules

256 MB modules




512 MB modules




Photo of the memory chips







256 MB module chips
512 MB module chips

Part Numbering System of Modules and Chips

Module Part Number

Part Numbering System of Samsung DDR SDRAM Modules:
http://www.samsung.com/Products/Semiconductor/Support/Label_CodeInfo/
DDR_SDRAM_Module.pdf

256 MB modules




Field Value Expansion
1 M Product code: M = memory module
2 3 Configuration: 3 = 4/8 byte DIMM
3-4 78 Data bit: 78 = x64, 240pin Unbuffered DIMM
5 T Feature, Voltage: T = DDR2, 1.8 V
6-7 32 Module depth: 32 = 32M
8 5 Number of bank in Comp., Interface, Refresh:
5 = 4 banks, SSTL(1.8V, 1.8V), 7.8 ms
9 3 Composition component: 3 = x8
10 F Component generation: F = 7th generation
11 G Package: G = FBGA
12 0 PCB revision and type: 0 = not available
13 (None)
14 C Power: C = normal, self ref.
15-16 E6 Speed: E6 = 3.0 ns, CL=5
17-18 0F (according to SPD data) Special handling (Customer List Reference)

512 MB modules




Field Value Expansion
1 M Product code: M = memory module
2 3 Configuration: 3 = 4/8 byte DIMM
3-4 78 Data bit: 78 = x64, 240pin Unbuffered DIMM
5 T Feature, Voltage: T = DDR2, 1.8 V
6-7 64 Module depth: 64 = 64M
8 5 Number of bank in Comp., Interface, Refresh:
5 = 4 banks, SSTL(1.8V, 1.8V), 7.8 ms
9 3 Composition component: 3 = x8
10 F Component generation: F = 7th generation
11 G Package: G = FBGA
12 0 PCB revision and type: 0 = not available
13 (None)
14 C Power: C = normal, self ref.
15-16 E6 Speed: E6 = 3.0 ns, CL=5
17-18 0F (according to SPD data) Special handling (Customer List Reference)

Chip Part Number

Part Numbering system of Samsung DDR2 memory chips:
http://www.samsung.com/Products/Semiconductor/Support/Label_CodeInfo/
DDR2_code.pdf

256/512MB module chips

Field Value Expansion
1 K Product code: M = memory module
2 4 Product type: 4 = DRAM
3 T Small classification: T = DDR2 SDRAM
4-5 56 Density: 56 = 256M
6-7 08 Bit organization: 08 = x8
8 3 Number of internal banks: 3 = 4 banks
9 Q Interface, VDD, VDDQ: Q = SSTL, 1.8V, 1.8V
10 F Generation: F = 7th generation
11 (None)
12 G Package: G = FBGA
13 C Temperature conditions, power consumption: C = normal
14-15 E6 Speed: E6 = DDR2-667 (333 MHz, tCL=5, tRCD=5, tRP=5)
16 (empty) Packing type reference
17-18 (empty) Customer (Customer List Reference)

Part Number expansions of the reviewed modules and chips (both modules are equipped with the same 32Mx8 memory chips) look almost impeccable, there are no conflicts between part number expansions of modules and chips.

SPD module chip data

Description of the SPD general standard:

Description of the SPD specific standard for DDR2:

SPD data of the 256MB modules

Parameter Byte Value Expansion
Fundamental Memory Type 2 08h DDR2 SDRAM
Number of Row Addresses on this assembly 3 0Dh 13 (RA0-RA12)
Number of Column Addresses on this assembly 4 0Ah 10 (CA0-CA9)
Number of DIMM Banks 5 60h 1 physical bank
Data Width of this assembly 6 40h 64 bit
Voltage Interface Level of this assembly 8 05h SSTL 1.8V
SDRAM Cycle time (tCK) at maximum supported CAS# latency (CL X) 9 30h 3.00 ns (333.3 MHz)
DIMM configuration type 11 00h Non-ECC
Refresh Rate/Type 12 82h 7.8125 ms — 0.5x reduced self-refresh
Primary SDRAM Width (organization type) of the memory module chips 13 08h x8
Error Checking SDRAM Width (organization type) of the memory chips in the ECC module 14 00h Not defined
Burst Lengths Supported (BL) 16 0Ch BL = 4, 8
Number of Banks on SDRAM Device 17 04h 4
CAS Latency (CL) 18 38h CL = 3, 4, 5
Minimum clock cycle (tCK) at reduced CAS latency (CL X-1) 23 3Dh 3.75 ns (266.7 MHz)
Minimum clock cycle (tCK) at reduced CAS latency (CL X-2) 25 50h 5.00 ns (200.0 MHz)
Minimum Row Precharge Time (tRP) 27 3Ch 15.0 ns
5, CL = 5
4, CL = 4
3, CL = 3
Minimum Row Active to Row Active delay (tRRD) 28 1Eh 7.5 ns
3, CL = 5
2, CL = 4
1.5, CL = 3
Minimum RAS to CAS delay (tRCD) 29 3Ch 15.0 ns
5, CL = 5
4, CL = 4
3, CL = 3
Minimum Active to Precharge Time (tRAS) 30 27h 39.0 ns
13, CL = 5
10, CL = 4
8, CL = 3
Module Bank Density 31 40h 256 MB
Write recovery time (tWR) 36 3Ch 15.0 ns
5, CL = 5
4, CL = 4
3, CL = 3
Internal write to read command delay (tWTR) 37 1Eh 7.5 ns
3, CL = 5
2, CL = 4
1.5, CL = 3
Internal read to precharge command delay (tRTP) 38 1Eh 7.5 ns
3, CL = 5
2, CL = 4
1.5, CL = 3
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 41, 40 36h, 00h 54.0 ns
18, CL = 5
14, CL = 4
11, CL = 3
SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) 42, 40 4Bh, 00h 75.0 ns
25, CL = 5
20, CL = 4
15, CL = 3
Maximum device cycle time (tCKmax) 43 80h 8.0 ns
SPD Revision 62 12h Revision 1.2
Checksum for Bytes 0-62 63 09h 9 (true)
Manufacturer’s JEDEC ID Code 64-71 CEh Samsung
Module Part Number 73-90 M3 78T3253FG0-CE6 0F
Module Manufacturing Date 93-94 04h, 44h year 2004, week 44
Module Serial Number 95-98 45h, 05h,
B3h, FFh
FFB30545h

SPD data of the 512MB modules

Parameter Byte Value Expansion
Fundamental Memory Type 2 08h DDR2 SDRAM
Number of Row Addresses on this assembly 3 0Dh 13 (RA0-RA12)
Number of Column Addresses on this assembly 4 0Ah 10 (CA0-CA9)
Number of DIMM Banks 5 61h 2 physical banks
Data Width of this assembly 6 40h 64 bit
Voltage Interface Level of this assembly 8 05h SSTL 1.8V
SDRAM Cycle time (tCK) at maximum supported CAS# latency (CL X) 9 30h 3.00 ns (333.3 MHz)
DIMM configuration type 11 00h Non-ECC
Refresh Rate/Type 12 82h 7.8125 ms — 0.5x reduced self-refresh
Primary SDRAM Width (organization type) of the memory module chips 13 08h x8
Error Checking SDRAM Width (organization type) of the memory chips in the ECC module 14 00h Not defined
Burst Lengths Supported (BL) 16 0Ch BL = 4, 8
Number of Banks on SDRAM Device 17 04h 4
CAS Latency (CL) 18 38h CL = 3, 4, 5
Minimum clock cycle (tCK) at reduced CAS latency (CL X-1) 23 3Dh 3.75 ns (266.7 MHz)
Minimum clock cycle (tCK) at reduced CAS latency (CL X-2) 25 50h 5.00 ns (200.0 MHz)
Minimum Row Precharge Time (tRP) 27 3Ch 15.0 ns
5, CL = 5
4, CL = 4
3, CL = 3
Minimum Row Active to Row Active delay (tRRD) 28 1Eh 7.5 ns
3, CL = 5
2, CL = 4
1.5, CL = 3
Minimum RAS to CAS delay (tRCD) 29 3Ch 15.0 ns
5, CL = 5
4, CL = 4
3, CL = 3
Minimum Active to Precharge Time (tRAS) 30 27h 39.0 ns
13, CL = 5
10, CL = 4
8, CL = 3
Module Bank Density 31 40h 256 MB
Write recovery time (tWR) 36 3Ch 15.0 ns
5, CL = 5
4, CL = 4
3, CL = 3
Internal write to read command delay (tWTR) 37 1Eh 7.5 ns
3, CL = 5
2, CL = 4
1.5, CL = 3
Internal read to precharge command delay (tRTP) 38 1Eh 7.5 ns
3, CL = 5
2, CL = 4
1.5, CL = 3
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 41, 40 36h, 00h 54.0 ns
18, CL = 5
14, CL = 4
11, CL = 3
SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) 42, 40 4Bh, 00h 75.0 ns
25, CL = 5
20, CL = 4
15, CL = 3
Maximum device cycle time (tCKmax) 43 80h 8.0 ns
SPD Revision 62 12h Revision 1.2
Checksum for Bytes 0-62 63 09h 9 (true)
Manufacturer’s JEDEC ID Code 64-71 CEh Samsung
Module Part Number 73-90 M3 78T6453FG0-CE6 0F
Module Manufacturing Date 93-94 04h, 45h year 2004, week 45
Module Serial Number 95-98 45h, 07h,
B7h, FFh
FFB70745h

SPD chip data of 256MB and 512MB modules looks practically identical — the only significant difference is in the number of banks, which completely corresponds to the appearance of reviewed samples (256MB modules have one bank, 512MB — two banks, a physical bank consists of 8 32M x8 chips). Samsung DDR2-667 modules can operate with three different CAS# latencies: 5, 4, and 3. These cases correspond to the following temporal (frequency) module operating modes — 3.0 ns (333 MHz), 3.75 ns (266 MHz), and 5.0 ns (200 MHz) — and to the most important timing schemes — 5-5-5-13 (note that the last timing tRAS is somewhat reduced relative to the "standard" value of 15), 4-4-4-10 (provided tRAS is rounded down) and 3-3-3-8 (the same condition). Interestingly, this memory uses the latest SPD Revision 1.2 of DDR2 modules (which is not yet published on the JEDEC web site). All the numbers — Part Number, manufacturing date and serial number — are written in full and correspond to the facts, which speaks of manufacturer's precision and creates the image of a high-quality product.

Testbed Configurations and Software

Testbed #1

  • CPU: Intel Pentium 4 3.6 GHz (Prescott E0, 1 MB L2)
  • Chipset: Intel 925X
  • Motherboard: Gigabyte 8ANXP-D, BIOS dated 06/07/2004
  • Memory: 2x256 MB Samsung DDR2-667 2x512 MB Samsung DDR2-667 in DDR2-533 mode
  • Video: Leadtek PX350 TDH, nVidia PCX5900
  • HDD: WD Raptor WD360, SATA, 10000 rpm, 36Gb
  • Drivers: nVidia Forceware 62.01, Intel Chipset Utility 6.2.1.1001, DirectX 9.0c

Testbed #2

  • CPU: Intel Pentium 4 3.6 GHz (Prescott E0, 1 MB L2)
  • Chipset: Intel 925X
  • Motherboard: MSI 925X Neo, BIOS dated 12/16/2004
  • Memory: 2x256 MB Samsung DDR2-667 2x512 MB Samsung DDR2-667 in DDR2-533 mode
  • Video: Leadtek PX350 TDH, nVidia PCX5900
  • HDD: WD Raptor WD360, SATA, 10000 rpm, 36Gb
  • Drivers: nVidia Forceware 62.01, Intel Chipset Utility 6.2.1.1001, DirectX 9.0c

Testbed #3

  • CPU: Intel Pentium 4 3.6 GHz (Prescott E0, 1 MB L2)
  • Chipset: Intel 925XE
  • Motherboard: ECS PF21 Extreme, BIOS F2 dated 12/07/2004
  • Memory: 2x256 MB Samsung DDR2-667 2x512 MB Samsung DDR2-667 in DDR2-533 mode
  • Video: Leadtek PX350 TDH, nVidia PCX5900
  • HDD: WD Raptor WD360, SATA, 10000 rpm, 36Gb
  • Drivers: nVidia Forceware 62.01, Intel Chipset Utility 6.2.1.1001, DirectX 9.0c

Testbed #4

  • CPU: Intel Pentium 4 3.6 GHz (Prescott E0, 1 MB L2)
  • Chipset: Intel 925XE
  • Motherboard: Gigabyte 8AENXP-D, BIOS F2 dated 01/04/2005
  • Memory: 2x256 MB Samsung DDR2-667 2x512 MB Samsung DDR2-667 in DDR2-533 mode
  • Video: Leadtek PX350 TDH, nVidia PCX5900
  • HDD: WD Raptor WD360, SATA, 10000 rpm, 36Gb
  • Drivers: nVidia Forceware 62.01, Intel Chipset Utility 6.2.1.1001, DirectX 9.0c

Testbed #5

  • CPU: Intel Pentium 4 3.6 GHz (Prescott E0, 1 MB L2) at 3.73 GHz (266 MHz x14)
  • Chipset: Intel 925XE
  • Motherboard: ECS PF21 Extreme, BIOS dated 12/07/2004
  • Memory: 2x256 MB Samsung DDR2-667 2x512 MB Samsung DDR2-667 in DDR2-533 mode
  • Video: Leadtek PX350 TDH, nVidia PCX5900
  • HDD: WD Raptor WD360, SATA, 10000 rpm, 36Gb
  • Drivers: nVidia Forceware 62.01, Intel Chipset Utility 6.2.1.1001, DirectX 9.0c

Testbed #6

  • CPU: Intel Pentium 4 3.6 GHz (Prescott E0, 1 MB L2) at 3.73 GHz (266 MHz x14)
  • Chipset: Intel 925XE
  • Motherboard: Gigabyte 8AENXP-D, BIOS F2 dated 01/04/2005
  • Memory: 2x256 MB Samsung DDR2-667 2x512 MB Samsung DDR2-667 in DDR2-533 mode
  • Video: Leadtek PX350 TDH, nVidia PCX5900
  • HDD: WD Raptor WD360, SATA, 10000 rpm, 36Gb
  • Drivers: nVidia Forceware 62.01, Intel Chipset Utility 6.2.1.1001, DirectX 9.0c

Test Results

Performance tests

Despite the 4-4-4-10 timing scheme mentioned above for DDR2-533 (obtained by rounding tRAS down), all motherboards set the 4-4-4-11 scheme by default in the first series of tests (Memory Timings: "by SPD"). Anyway, these memory modules, as well as most other modules, ignore the latter parameter in chipset settings, which is demonstrated by the following test series.

Testing 256MB modules

Parameter Testbed 1 Testbed 2 Testbed 3 Testbed 4 Testbed 5* Testbed 6*
Timings
4-4-4-11
4-4-4-11
4-4-4-11
4-4-4-11
4-4-4-11
4-4-4-11
Average memory read bandwidth, MB/sec
4987
5548
5551
5570
6926
6840
Average memory write bandwidth, MB/sec
1929
2017
1983
1946
2248
2252
Max. memory read bandwidth, MB/sec
6474
6376
6446
6394
8214
8045
Max. memory write bandwidth, MB/sec
4287
4265
4256
4287
5694
5662
Minimum Pseudo-Random Access Latency, ns
47.7
50.1
50.3
50.1
43.0
43.5
Maximum Pseudo-Random Access Latency, ns
54.4
57.5
57.7
57.4
50.3
50.8
Minimum Random Access Latency**, ns
117.6
117.8
118.1
117.1
105.8
106.6
Maximum Random Access Latency**, ns
135.2
135.5
136.1
134.7
123.3
124.3
Minimum Pseudo-Random Access Latency, ns
(without hardware prefetch)
77.9
78.2
78.5
77.4
66.4
67.2
Maximum Pseudo-Random Access Latency, ns
(without hardware prefetch)
97.9
96.9
99.1
96.2
87.0
87.9
Minimum Random Access Latency**, ns
(without hardware prefetch)
118.5
118.7
119.1
117.9
106.4
107.3
Maximum Random Access Latency**, ns
(without hardware prefetch)
138.5
138.2
139.1
137.3
126.0
127.1

*266.7 MHz FSB frequency
**16MB block size

Testing 512MB modules

Parameter Testbed 1 Testbed 2 Testbed 3 Testbed 4 Testbed 5* Testbed 6*
Timings
4-4-4-11
4-4-4-11
4-4-4-11
4-4-4-11
4-4-4-11
4-4-4-11
Average memory read bandwidth, MB/sec
5001
5584
5586
5608
6978
6949
Average memory write bandwidth, MB/sec
2403
2418
2400
2424
2720
2673
Max. memory read bandwidth, MB/sec
6484
6442
6458
6433
8288
8184
Max. memory write bandwidth, MB/sec
4287
4265
4256
4287
5695
5688
Minimum Pseudo-Random Access Latency, ns
47.6
50.0
50.2
49.9
43.0
43.0
Maximum Pseudo-Random Access Latency, ns
54.4
57.4
57.5
57.2
50.2
50.2
Minimum Random Access Latency**, ns
116.5
116.7
117.1
116.1
104.4
104.6
Maximum Random Access Latency**, ns
134.3
134.3
135.1
133.7
122.0
121.8
Minimum Pseudo-Random Access Latency, ns
(without hardware prefetch)
77.9
78.1
78.3
77.5
66.4
66.3
Maximum Pseudo-Random Access Latency, ns
(without hardware prefetch)
97.8
96.9
97.2
96.3
86.7
86.8
Minimum Random Access Latency**, ns
(without hardware prefetch)
117.3
117.4
117.8
116.9
105.0
105.2
Maximum Random Access Latency**, ns
(without hardware prefetch)
137.1
137.5
137.5
136.5
123.8
124.1

*266.7 MHz FSB frequency
**16MB block size

Interestingly, the two-bank 512MB modules demonstrate some advantage over the single-bank 256MB samples in most parameters (Average Read and Write Memory Bandwidth, in particular). The fact that Gigabyte 8ANXP-D on the i925X chipset (Testbed #1) is significantly outperformed in average memory read bandwidth by other motherboards based on i925X/XE series chipsets can be explained by an older BIOS version, which most likely does not enable Performance Acceleration Technology (PAT) in the memory controller. MSI 925X Neo (Testbed #2), ECS PF21 Extreme (Testbed #3) and Gigabyte 8AENXP-D (Testbed #4) motherboards demonstrate approximately equal results when operating at the standard 200 MHz FSB. When the last two motherboards operate at 266 MHz FSB, ECS PF21 Extreme (Testbed #5) demonstrates a small advantage over Gigabyte 8AENXP-D (Testbed #6).

Stability tests

Timing values, except for tCL, were changed "on the fly" thanks to the built-in RMMA feature that allows dynamic changes of memory settings supported by a chipset. Memory operation stability was evaluated in our specially developed utility, which will soon be released as a stand-alone application and will come shipped with RMMA.

Testing 256MB modules

Parameter Testbed 1 Testbed 2 Testbed 3 Testbed 4 Testbed 5* Testbed 6*
Timings
3-4-4
3-3-4
3-4-4
3-4-4
3-4-4
3-4-4
Average memory read bandwidth, MB/sec
5169
5645
5593
5674
7042
7003
Average memory write bandwidth, MB/sec
2018
2254
2197
2032
2472
2292
Max. memory read bandwidth, MB/sec
6506
6426
6466
6453
8245
8125
Max. memory write bandwidth, MB/sec
4287
4265
4256
4287
5694
5667
Minimum Pseudo-Random Access Latency, ns
46.0
48.5
48.8
48.1
41.3
41.4
Maximum Pseudo-Random Access Latency, ns
52.3
55.3
55.6
54.9
47.9
48.2
Minimum Random Access Latency**, ns
114.4
110.4
115.5
114.2
102.4
103.4
Maximum Random Access Latency**, ns
131.8
129.0
132.8
131.5
119.8
121.2
Minimum Pseudo-Random Access Latency, ns
(without hardware prefetch)
76.0
75.9
76.8
75.7
64.0
64.2
Maximum Pseudo-Random Access Latency, ns
(without hardware prefetch)
95.4
95.1
97.3
94.2
83.3
83.4
Minimum Random Access Latency**, ns
(without hardware prefetch)
115.3
111.0
116.2
114.8
103.4
103.8
Maximum Random Access Latency**, ns
(without hardware prefetch)
135.1
130.6
136.4
134.4
121.4
122.7

*266.7 MHz FSB frequency
**16MB block size

Testing 512MB modules

Parameter Testbed 1 Testbed 2 Testbed 3 Testbed 4 Testbed 5* Testbed 6*
Timings
3-4-4
3-3-4
3-4-4
3-4-4
3-4-4
3-4-4
Average memory read bandwidth, MB/sec
5188
5674
5637
5683
7114
7009
Average memory write bandwidth, MB/sec
2429
2369
2396
2452
2722
2698
Max. memory read bandwidth, MB/sec
6507
6430
6481
6465
8341
8153
Max. memory write bandwidth, MB/sec
4287
4265
4256
4287
5695
5667
Minimum Pseudo-Random Access Latency, ns
46.0
48.5
48.6
48.1
41.0
41.4
Maximum Pseudo-Random Access Latency, ns
52.4
55.3
55.5
55.0
47.8
48.2
Minimum Random Access Latency**, ns
113.4
109.4
114.3
113.2
101.2
102.3
Maximum Random Access Latency**, ns
130.7
127.9
131.7
130.3
118.7
119.8
Minimum Pseudo-Random Access Latency, ns
(without hardware prefetch)
76.1
76.4
76.7
75.5
63.5
64.2
Maximum Pseudo-Random Access Latency, ns
(without hardware prefetch)
95.1
95.1
95.5
94.1
82.5
83.4
Minimum Random Access Latency**, ns
(without hardware prefetch)
114.2
110.4
115.0
113.8
101.8
102.7
Maximum Random Access Latency**, ns
(without hardware prefetch)
134.3
129.7
134.4
133.2
119.5
120.9

* 266.7 MHz FSB frequency
**16 MB block size

The minimum timings (3-4-4) available in both module types in DDR2-533 mode for most motherboards are quite average, especially considering that the reviewed modules are designed for the DDR2-667 mode. Besides, both 256MB and 512MB modules allow the 3-3-4 timing scheme on MSI 925X Neo (Testbed #2), which has immediately resulted in the random access latency reduced by approximately 5 ns relative to the values obtained on other motherboards, all other conditions being equal (Testbeds #1, #3, and #4).

Bottom line

Tested samples of 256MB and 512MB Samsung DDR2-667 modules provide good compatibility with the motherboard models on i925X and i925XE chipsets that we used, good performance (memory bandwidth and latencies are typical for high-performance modules operating in DDR2-533 mode), and moderate timing overclocking potential (they operate with tCL reduced by one relative to the nominal value on all motherboards used in our review). Besides, we should note the precise approach of the manufacturer to designations on modules, chips and to the SPD chip data, which produces an impression of high-quality products.



Dmitri Besedin (dmitri_b@ixbt.com)
March 30, 2005


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