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Memory Module Analysis. Part 7: Patriot DDR400+XBLK Modules and the First Test Results in DDR-500 Mode

April 5, 2006

We proceed with the series of articles, dedicated to the low level analysis of the most important characteristics of DDR memory modules using our RightMark Memory Analyzer test package. Today we are going to review a pair of 1GB modules (specially matched for dual channel mode) of the DDR-400 series +XBL (eXtreme Bandwidth and Latency), intended for overclockers, enthusiasts, and gamers. Peculiarities of this series are low latencies in the native official DDR-400 mode (2-2-2-5) as well as support for up to 266 MHz, that is in unofficial DDR-433, DDR-466, DDR-500, and DDR-533 modes.

Manufacturer Information

Module manufacturer: Patriot Memory (Division of PDP Systems, Inc.)
Manufacturer of module chips: unknown
Web site of the module manufacturer: http://www.patriotmem.com

Module Exterior

Photo of the memory module

Exterior of the modules, covered with a usual aluminum red heatsink, is quite typical of DDR Patriot memory modules.

Module Part Number

The manufacturer's web site does not publish the DDR Part Number expansion of +XBL series memory modules. Datasheet on modules with Part Number PDC1G3200+XBLK specifies that the product is a pair of matched DDR-400 modules of the total capacity of 1GB, which can operate in a wide range of frequencies — from 200 MHz (DDR-400, PC3200) to 266 MHz (DDR-533, PC4200). In the nominal DDR-400 mode these products are characterized by very low latencies — 2-2-2-5. Recommended timings and voltages for each mode are published in the table below. The manufacturer notes that these modules are 100% tested in each mode under specified conditions, that is the company actually guarantees operation stability in all listed modes.

High-performance mode Timings Voltage
PC3200 (DDR-400) 2-2-2-5 2.6 — 2.7V
PC3500 (DDR-433) 2-3-3-6 2.6 — 2.7V
PC3700 (DDR-466) 2-3-3-6 2.7 — 2.8V
PC4000 (DDR-500) 2.5-3-3-7 2.75 — 2.85V
PC4200 (DDR-533) 3-4-4-8 2.75 — 2.85V

SPD chip data

Description of the general SPD standard:
JEDEC Standard No. 21-C, 4.1.2 - SERIAL PRESENCE DETECT STANDARD, General Standard

Description of the specific SPD standard for DDR:
JEDEC Standard No. 21-C, — Appendix D, Rev. 1.0: SPD’s for DDR SDRAM

Parameter Bytes Value Expansion
Fundamental Memory Type 2 07h DDR SDRAM
Number of Row Addresses on this assembly 3 0Dh 13 (RA0-RA12)
Number of Column Addresses on this assembly 4 0Ah 10 (CA0-CA9)
Number of DIMM Banks 5 02h 2 physical banks
Data Width of this assembly 6, 7 40h, 00h 64 bit
Voltage Interface Level of this assembly 8 04h SSTL 2.5V
SDRAM Cycle time (tCK) at maximum supported CAS# latency (CL X) 9 50h 5.00 ns (200.0 MHz)
DIMM configuration type 11 00h Non-ECC
Refresh Rate/Type 12 82h 7.8125 ms — 0.5x reduced self-refresh
Primary SDRAM Width (organization type) of the memory module chips 13 08h x8
Error Checking SDRAM Width (organization type) of the memory chips in the ECC module 14 00h Not defined
Burst Lengths Supported (BL) 16 0Eh BL = 2, 4, 8
Number of Banks on SDRAM Device 17 04h 4
CAS Latency (CL) 18 04h CL = 2.0
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-0.5) 23 50h 5.00 ns (200.0 MHz)
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-1.0) 25 00h Not defined
Minimum Row Precharge Time (tRP) 27 28h 10.0 ns
2, CL = 2.0
Minimum Row Active to Row Active delay (tRRD) 28 28h 10.0 ns
2, CL = 2.0
Minimum RAS to CAS delay (tRCD) 29 28h 10.0 ns
2, CL = 2.0
Minimum Active to Precharge Time (tRAS) 30 19h 25.0 ns
5, CL = 2.0
Module Bank Density 31 40h 256 MB
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 41 37h 55.0 ns
11, CL = 2.0
SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) 42 41h 65.0 ns
13, CL = 2.0
Maximum device cycle time (tCKmax) 43 28h 10.0 ns
SPD Revision 62 00h Not defined
Checksum for Bytes 0-62 63 F4h 244 (true)
Manufacturer’s JEDEC ID Code (only the first significant bytes are shown) 64-71 7Fh, 7Fh,
7Fh, 7Fh,
PDP Systems
Module Part Number 73-90 01h, 64h,
Module Manufacturing Date 93-94 00h, 00h Not defined
Module Serial Number 95-98 00h, 00h,
00h, 00h
Not defined

SPD contents look unusual. According to Byte 18, these modules support only one CAS# latency - 2. This CAS# latency (CL X) corresponds to the cycle time of 5 ns, that is DDR-400 mode. The timings scheme for this case matches the specification value — 2-2-2-5, which theoretically should guarantee that BIOS versions in the majority of motherboards would set these very timings by default. Nevertheless, for some unknown reason Byte 23 contains the second reduced CAS# latency (CL X-0.5, that is tCL = 1.5, unofficial for DDR), which still corresponds to the same cycle time of 5 ns, that is DDR-400 mode. Timings for the second case (if it had been supported by the standard) would have looked like 1.5-2-2-5. Speaking of deviations from the standard, we can note more peculiarities of the SPD contents in these modules - undefined SPD Revision Number 0.0, no Part Numbering information (just a sequence of bytes 01h, 64h, and 08h, which cannot be converted into text), as well as the manufacturing date and serial number. Nevertheless, Manufacturer’s JEDEC ID Code (PDP Systems) is specified correctly.

Testbed configurations

Testbed 1

  • CPU: AMD Athlon 64 4000+, 2.4 GHz (ClawHammer, 1 MB L2)
  • Chipset: NVIDIA nForce4 SLI X16
  • Motherboard: ASUS A8N32SLI Deluxe, BIOS 0502 dated 10/06/2005
  • Memory: 2x512 MB Patriot DDR-400+XBLK (in DDR-400 mode)

Testbed 2

  • CPU: AMD Athlon 64 4000+, 2.4 GHz (ClawHammer, 1 MB L2)
  • Chipset: NVIDIA nForce4 SLI X16
  • Motherboard: ASUS A8N32SLI Deluxe, BIOS 0502 dated 10/06/2005
  • Memory: 2x512 MB Corsair XMS PC3200, DDR-400

Testbed 3

  • CPU: AMD Athlon 64 3500+, 2.0 — 2.2 GHz (Venice, 512 KB L2)
  • Chipset: ATI Radeon Xpress 200 CrossFire
  • Motherboard: ECS RD480-A939, BIOS 1.1b dated 13/02/2006
  • Memory: 2x512 MB Patriot DDR-400+XBLK (in DDR-500 mode)

Testbed 4

  • CPU: AMD Athlon 64 FX-57, 2.0 — 2.8 GHz (San Diego, 1 MB L2)
  • Chipset: ATI Radeon Xpress 200 CrossFire
  • Motherboard: ECS RD480-A939, BIOS 1.1b dated 13/02/2006
  • Memory: 2x512 MB Patriot DDR-400+XBLK (in DDR-500 mode)

Test Results

Tests in DDR-400 mode

The first series of tests was carried out in the standard DDR-400 mode (Testbed 1). For comparison purposes, we performed the same tests with a couple of 512 MB Corsair DDR-400 modules (used in our test lab for a long time already) with the same low timings 2-2-2-5 (Testbed 2).

Parameter Testbed 1 Testbed 2
Timings 2-2-2-5 2-2-2-5
Average memory read bandwidth, MB/sec 4385 4387
Average memory write bandwidth, MB/sec 2562 2541
Max. memory read bandwidth, MB/sec 6399 6415
Max. memory write bandwidth, MB/sec 6196 6194
Minimum Pseudo-Random Access Latency, ns 31.4 31.5
Maximum Pseudo-Random Access Latency, ns 35.2 35.3
Minimum Random Access Latency*, ns 57.9 57.9
Maximum Random Access Latency*, ns 62.1 62.1

*16 MB block size

These test results are obvious and don't need any comments: DDR-400 modules of the +XBLK series from Patriot offer excellent performance in the standard DDR-400 mode. They are no worse or even identical to the high-speed Corsair DDR-400 modules with 2-2-2-5 timings in many parameters.

This time we shall not carry out stability tests, that is tests of the modules in more extreme conditions — with overclocked timings, for a simple reason that 2-2-2-5 timings on the AMD Athlon 64 platform cannot be reduced any further. Instead, we proceed to analyzing results of a much more interesting series of tests in "DDR-500" mode.

Tests in DDR-500 mode

We write this mode in inverted commas for a reason — first of all, there is no strict correspondence to it here (that is memory modules operating at 250 MHz); secondly, memory frequency depends on a processor clock.

What are our reasons for running these tests? As is well known, the latest revision "E" of AMD Athlon 64/FX processors supports new unofficial (they are not mentioned in AMD documentation, probably because these modes are not specified by the JEDEC standard) memory modes — at the memory clock limit of 233 MHz and 250 MHz, which can be set in BIOS of the latest motherboards, for example, in ECS RD480-A939. It's a "limit", because the real frequency depends on the clock of a processor/memory controller (we get it by dividing CPU clock by an integer value). As a rule, it's always lower than this limit (MemClk limit).

Thus, thanks to the latest revision of AMD processors and proper BIOS support from motherboards we can now really use faster non-standard DDR memory without overclocking other components of the system by raising FSB frequency. As the modules under review support frequencies of up to 266 MHz (DDR-533), we immediately decided to use them for testing new operating modes of the AMD64 dual channel memory controller, integrated into AMD Athlon 64/FX processors.

So everything looks just fine in theory, but in fact it turns out a tad different from what we have expected. The problem lies in the above mentioned inevitable memory frequency dependence on a CPU clock - memory frequency is obtained by dividing CPU clock by some integer value. On one hand, it results in variable memory frequency in time, when the CPU clock is changed dynamically by the convenient and useful AMD Cool`n'Quiet technology, or (if this technology is not used for some reason) just in the dependence of memory frequency on a given processor model, designed for operation at a given maximum frequency. On the other hand (which is more important), tests reveal that in the unofficial DDR-500 mode processors often wrongly select a greater divider (corresponding to a lower memory frequency). You can see all this in the table below.

Parameter Testbed 3 Testbed 4
CPU clock, MHz 2200 2000 2800 2400 2200 2000
Expected memory frequency, MHz
(memory frequency divider)
Actual memory frequency, MHz
(memory frequency divider),
according to the test results
Timings 2.5-3-3-8 2.5-3-3-8 2.5-3-3-8 2.5-3-3-8 2.5-3-3-8 2.5-3-3-8
Average memory read bandwidth, MB/sec 3730 3809 4166 3922 3651 3743
Average memory write bandwidth, MB/sec 2838 2719 3056 2992 2749 2921
Max. memory read bandwidth, MB/sec 6915 7029 7193 7331 6695 6909
Max. memory write bandwidth, MB/sec 6425 5825 7088 6902 6323 5755
Minimum Pseudo-Random Access Latency, ns 25.7 25.3 23.7 24.4 26.1 25.6
Maximum Pseudo-Random Access Latency, ns 29.8 29.3 27.0 28.4 30.2 29.6
Minimum Random Access Latency*, ns 63.7 61.8 58.4 60.0 64.5 62.5
Maximum Random Access Latency*, ns 68.1 64.6 62.0 63.7 69.0 65.3

*16 MB block size

At first, let's analyze test results for AMD Athlon 64 3500+ (Testbed 3). The expected memory frequency in the standard mode (2.2 GHz) might have been 244.4 (2200 / 9) MHz. But in fact the system selects a greater divider (/10), which reduces its frequency to 220 MHz (as if limited to DDR-466 — by the way, our test results in this mode were indeed identical). In particular, the proof of that is the maximum real memory read bandwidth (6915 MB/s), while the theoretical bandwidth of a 244 MHz memory bus is 7820 MB/s. Maximum theoretical bandwidth of the 220 MHz memory bus (7040 MB/s) turns out much closer to the test result, that is this test demonstrates 98% utilization efficiency of the memory bus, quite typical for this platform class.

The same picture can bee seen, when the CPU clock is reduced to 2 GHz. The expected memory frequency in this case might have reached the limit — 250 (2000 / 8) MHz. Nevertheless, the system again selects a greater divider here (/9), which is again closer to DDR-466 rather than to DDR-500 — so the real memory frequency turns out to be 222.2 MHz. As we can see, it's accompanied by further growth of the maximum real memory read bandwidth to 7029 MB/s.

Let's proceed to test results of the Athlon 64 FX-57 processor (Testbed 4), which allows to use a much wider frequency range. The standard mode (2800 MHz) allows to reach a slightly higher memory frequency compared to what we have seen above. Moreover, this time the real memory frequency matches the expected value — 233.3 MHz (2800 / 12). Maximum real memory bandwidth in this test is 7193 MB/s, that is approximately 96% of the theoretical maximum (7467 MB/s).

We managed to get a still higher memory frequency, when the CPU clock was reduced to 2.4 GHz. And again the expected memory frequency (240 MHz = 2400 / 10) matches the real value, which manifests itself as a higher maximum real memory bandwidth (7331 MB/s). Theoretical maximum memory bandwidth for 240 MHz is 7680 MB/s, that is the utilization efficiency of the memory bus in this test is approximately 95.5%. It should be noted that it drops as the memory frequency grows, which probably reflects the real limit of DDR memory efficiency as such.

Reducing the clock of the Athlon 64 FX-57 processor to 2200 MHz and then to 2000 MHz leads to the results, which are similar to what we have seen above for the Athlon 64 3500+ processor (probably the only difference is that the maximum real memory bandwidth of the Athlon 64 FX-57 at these frequencies is a tad lower for unknown reasons). Namely, the system sets much lower memory frequencies — 220 MHz and 222 MHz versus the expected 244 MHz and 250 MHz, correspondingly. We have an impression that limiting memory frequency to 250 MHz in the AMD64 memory controller settings actually limits memory frequency to 240 MHz — we have reached this frequency limit in real conditions.

Bottom line

These days, Patriot DDR-400+XBLK modules are typical high-performance DDR modules, as there already exist top 2GB high-performance modules of the average capacity, which are no slower than the old-line 1GB pair of Corsair DDR-400 modules.

At the same time, unlike the latter, Patriot DDR-400+XBLK officially supports faster modes — from DDR-433 to DDR-533 inclusive, which we partially tested in our today's review. Let's say a few final words about these tests, as we didn't overclock the bus frequency of system components, but used new unofficial modes of the integrated memory controller of AMD Athlon 64/FX (of the latest Revision E), which formally allow to use memory frequencies below 250 MHz.

So, Patriot DDR-400+XBLK modules at increased voltage (2.75V) can really operate stably at up to 240 MHz (we just didn't test higher frequencies), reaching a tad lower utilization efficiency of the memory bus bandwidth compared to the DDR-400 mode. But it's still very high (about 95%). Nevertheless, performance of the memory controller in AMD64 processors is disappointing - in some cases it uses higher memory frequency dividers than necessary. In this connection the real memory frequency falls between 220-240 MHz, depending on a CPU clock, and cannot possibly reach 250 MHz (formally possible).

At the same time, as non-standard memory frequency dividers still pertain to tweaking (using undocumented features), they are most often used only by enthusiasts, accompanied by classic bus overclocking. In this case, new dividers are indeed of great help. For example, in case of top processors, which cannot offer great overclocking potential, so that the elite memory remain "underoverclocked". In this case, having selected a higher frequency range (smaller divider), you can overclock memory to a higher degree and have more chances to use even the best modules to the full extent (aggressive dividers corresponding to 250 MHz are not required in this case).

Dmitri Besedin (dmitri_b@ixbt.com)
Dmitry Vladimirovich (lpt@ixbt.com)
April 5, 2006

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