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Memory Module Analysis. Part 26: High-Speed Titanium and SLI-Ready Memory Modules from OCZ (PC2-6400, PC2-7200, and PC2-8000)

March 27, 2007



We proceed with the analysis of the most important characteristics of high-performance DDR2 memory modules using our RightMark Memory Analyzer. Today we are going to review high-speed solutions from OCZ — three dual-channel 2-GB memory kits, Titanium and SLI-Ready series, PC2-6400, PC2-7200 and PC2-8000:

  • OCZ DDR2 PC2-6400 Titanium EPP-Ready (OCZ2T8002GK, DDR2-800 4-4-4-1T)
  • OCZ DDR2 PC2-7200 SLI-Ready Edition (OCZ2N900SR2GK, DDR2-900 4-4-3-2T)
  • OCZ DDR2 PC2-8000 Titanium Alpha VX2 (OCZ2TA1000VX22GK, DDR2-1000 4-4-4-2T)

Manufacturer Information

Module manufacturer: OCZ Technology
Manufacturer of module chips: unknown
Web site of the module manufacturer: http://www.ocztechnology.com/products/ddr2/

Exterior

OCZ DDR2 PC2-6400




OCZ DDR2 PC2-7200




OCZ DDR2 PC2-8000




Part Number

The manufacturer's web site does not publish the DDR2 Part Number expansion (we found out just an outdated manual about DDR memory modules). So we'll confine ourselves to a brief description of the modules, published on corresponding product web pages.

OCZ DDR2 PC2-6400




The new OCZ DDR2 PC2-6400 Titanium EPP-Ready modules are equipped with Enhanced Performance Profiles (EPP) to optimize the modules' performance on current nForce® 590 SLI-based motherboards. EPP profiles are programmed to boot at 800MHz DDR2 with supremely fast timings of 4-4-4 1T, that is the modules are capable of accepting one command per clock cycle (1T) so that memory performance is increased by a considerable amount. Each module comes equipped with integrated titanium-mirrored XTC (Xtreme Thermal Convection) heatspreaders for the most efficient heat dissipation.

OCZ DDR2 PC2-7200




OCZ DDR2 PC2-7200 SLI-Ready Edition modules also support EPP. They are programmed to boot at DDR2-900 with 4-4-3 timings. According to the manufacturer, these modules come equipped with exclusive NVIDIA XTC heatspreaders for the most efficient heat dissipation and a look that stands out like its performance.

OCZ DDR2 PC2-8000




Unlike the first two representatives, OCZ DDR2 PC2-8000 Titanium Alpha VX2 modules lack EPP support. These modules belong to the proprietary Voltage Xtreme family, designed to operate at a high voltage (to obtain higher speed than available at the usual voltage level). This model is designed for DDR2-1000 and 4-4-4 timings owing to the raised voltage of 2.3V. It's positioned as a high-end solution for hardcore gamers and overclockers. Titanium-mirrored scratch-resistant XTC heatspreaders are also an exclusive solution, this time — with their colors (see the photo). Each Titanium Alpha module has a unique color and changes its hue depending on lighting and angle of view.

SPD chip data

Description of the general SPD standard:

Description of the specific SPD standard for DDR2:

EPP Standard Description:

OCZ DDR2 PC2-6400

Parameter Byte Value Expansion
Fundamental Memory Type 2 08h DDR2 SDRAM
Number of Row Addresses on this assembly 3 0Eh 14 (RA0-RA13)
Number of Column Addresses on this assembly 4 0Ah 10 (CA0-CA9)
Number of DIMM Banks 5 61h 2 physical banks
Data Width of this assembly 6 40h 64 bit
Voltage Level 8 05h SSTL 1.8V
SDRAM Cycle time (tCK) at maximum supported CAS# latency (CL X) 9 25h 2.50 ns (400.0 MHz)
DIMM configuration type 11 00h Non-ECC
Refresh Rate/Type 12 82h 7.8125 ms — 0.5x reduced self-refresh
Primary SDRAM Width (organization type) of the memory module chips 13 08h x8
Error Checking SDRAM Width (organization type) of the memory chips in the ECC module 14 00h Not defined
Burst Lengths Supported (BL) 16 0Ch BL = 4, 8
Number of Banks on SDRAM Device 17 04h 4
CAS Latency (CL) 18 38h CL = 5, 4, 3
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-1) 23 30h 3.00 ns (333.3 MHz)
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-2) 25 37h 3.70 ns (270.3 MHz)
Minimum Row Precharge Time (tRP) 27 32h 12.5 ns
5.00, CL = 5
4.17, CL = 4
3.37, CL = 3
Minimum Row Active to Row Active delay (tRRD) 28 28h 10.0 ns
4.00, CL = 5
3.33, CL = 4
2.70, CL = 3
Minimum RAS to CAS delay (tRCD) 29 32h 12.5 ns
5.00, CL = 5
4.17, CL = 4
3.37, CL = 3
Minimum Active to Precharge Time (tRAS) 30 25h 37.0 ns
14.80, CL = 5
12.33, CL = 4
10.00, CL = 3
Module Bank Density 31 80h 512 MB
Write recovery time (tWR) 36 3Ch 15.0 ns
6.00, CL = 5
5.00, CL = 4
4.05, CL = 3
Internal write to read command delay (tWTR) 37 1Eh 7.5 ns
3.00, CL = 5
2.50, CL = 4
2.02, CL = 3
Internal read to precharge command delay (tRTP) 38 1Eh 7.5 ns
3.00, CL = 5
2.50, CL = 4
2.02, CL = 3
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 41, 40 37h, 00h 55.0 ns
22.00, CL = 5
18.33, CL = 4
14.86, CL = 3
SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) 42, 40 69h, 00h 105.0 ns
42.00, CL = 5
35.00, CL = 4
28.38, CL = 3
Maximum device cycle time (tCKmax) 43 80h 8.0 ns
SPD Revision 62 23h Revision 2.3(?)
Checksum for Bytes 0-62 63 BFh 191 (true)
Manufacturer’s JEDEC ID Code 64-71 7Fh, 7Fh,
7Fh, 7Fh,
B0h
OCZ
Module Part Number 73-90 - OCZ2T8001G
Module Manufacturing Date 93-94 06h, 26h Year 2006, Week 38
Module Serial Number 95-98 00h, 00h,
00h, 00h
Not defined

According to SPD, supported CAS# latencies are 5, 4, and 3. The first value (CL X = 5) corresponds to the cycle time of 2.5 ns (400 MHz), i.e. DDR2-800. Not all timings for this case are integer. This scheme can be written as 5-5-5-14.8. Considering the most probable rounding up, it corresponds to the standard 5-5-5-15 timings. Reduced CAS# latency (CL X-1 = 4) corresponds to DDR2-667 (3.0 ns cycle time, 333.3 MHz) with noninteger 4-4.17-4.17-12.33 timings, which can be rounded up to 4-5-5-13. And finally, CAS# latency reduced by two (CL X-2 = 3) corresponds to slightly wrong but wide-spread DDR2-533 mode at the 3.7 ns cycle time (270.3 MHz) instead of nominal 3.75 ns (266.7 MHz). Timings for this case look like 3-3.37-3.37-10, rounded up to 3-4-4-10.

Manufacturer's JEDEC ID Code, manufacturing date, and Part Number of the module are correct. But there is no information about its serial number. Besides, we don't like the looks of the strange SPD Revision 23h, which formally corresponds to nonexistent Revision 2.3.

As these modules support EPP, let's analyze information from this "non-standard" part of SPD, represented by SPD Bytes 99-127.

Parameter Byte(s) (bits) Value Expansion
EPP Identifier String
99-101
4E566Dh
EPP SPD Support
EPP Profile Type Identifier
102
A1h
Abbreviated profiles
Profile for Optimal Performance
103 (1:0)
00h
Profile 0
Enabled Profiles
103 (7:4)
01h
Profile 0: available
Profile 1: not available
Profile 2: not available
Profile 3: not available
Profile 0
Voltage Level
104 (6:0)
08h
2.0 V
Addr CMD rate
104 (7)
00h
1T
Cycle time (tCK)
105
25h
2.50 ns (400.0 MHz)
CAS# latency (tCL)
106
10h
4
Minimum RAS to CAS delay (tRCD)
107
28h
10.0 ns (4.0)
Minimum Row Precharge Time (tRP)
108
28h
10.0 ns (4.0)
Minimum Active to Precharge Time (tRAS)
109
25h
37.0 ns (14.8)

EPP data are presented in the form of abbreviated profiles. There can be maximum four of them, while there is actually information only about the first profile (Profile 0), which is naturally marked as optimal. This abbreviated profile contains scarce information, which is published in the above table completely. The data include memory voltage — 2.0 V, address command rate (1T), cycle time (2.5 ns, 400 MHz memory bus, DDR2-800), and standard timings (4-4-4-14.8, rounded up to 4-4-4-15). The abbreviated EPP lacks additional parameters to fine-tune timings and electrical characteristics of memory. In our opinion, it discredits its main advantages. The manufacturer probably didn't pay proper attention to tweaking these characteristics. We'll see the consequences below, in the course of our module analysis. As for now, let's proceed to SPD of the next representative.

OCZ DDR2 PC2-7200

Parameter Byte Value Expansion
Fundamental Memory Type 2 08h DDR2 SDRAM
Number of Row Addresses on this assembly 3 0Eh 14 (RA0-RA13)
Number of Column Addresses on this assembly 4 0Ah 10 (CA0-CA9)
Number of DIMM Banks 5 61h 2 physical banks
Data Width of this assembly 6 40h 64 bit
Voltage Level 8 05h SSTL 1.8V
SDRAM Cycle time (tCK) at maximum supported CAS# latency (CL X) 9 25h 2.50 ns (400.0 MHz)
DIMM configuration type 11 00h Non-ECC
Refresh Rate/Type 12 82h 7.8125 ms — 0.5x reduced self-refresh
Primary SDRAM Width (organization type) of the memory module chips 13 08h x8
Error Checking SDRAM Width (organization type) of the memory chips in the ECC module 14 00h Not defined
Burst Lengths Supported (BL) 16 0Ch BL = 4, 8
Number of Banks on SDRAM Device 17 04h 4
CAS Latency (CL) 18 38h CL = 5, 4, 3
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-1) 23 3Dh 3.75 ns (266.7 MHz)
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-2) 25 00h Not defined
Minimum Row Precharge Time (tRP) 27 32h 12.5 ns
5.00, CL = 5
3.33, CL = 4
Not defined, CL = 3
Minimum Row Active to Row Active delay (tRRD) 28 1Eh 7.5 ns
3.00, CL = 5
2.00, CL = 4
Not defined, CL = 3
Minimum RAS to CAS delay (tRCD) 29 32h 12.5 ns
5.00, CL = 5
3.33, CL = 4
Not defined, CL = 3
Minimum Active to Precharge Time (tRAS) 30 25h 37.0 ns
14.80, CL = 5
9.87, CL = 4
Not defined, CL = 3
Module Bank Density 31 80h 512 MB
Write recovery time (tWR) 36 3Ch 15.0 ns
6.00, CL = 5
4.00, CL = 4
Not defined, CL = 3
Internal write to read command delay (tWTR) 37 1Eh 7.5 ns
3.00, CL = 5
2.00, CL = 4
Not defined, CL = 3
Internal read to precharge command delay (tRTP) 38 1Eh 7.5 ns
3.00, CL = 5
2.00, CL = 4
Not defined, CL = 3
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 41, 40 37h, 00h 55.0 ns
22.00, CL = 5
14.86, CL = 4
Not defined, CL = 3
SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) 42, 40 69h, 00h 105.0 ns
42.00, CL = 5
28.38, CL = 4
Not defined, CL = 3
Maximum device cycle time (tCKmax) 43 80h 8.0 ns
SPD Revision 62 12h Revision 1.2
Checksum for Bytes 0-62 63 2Ah 42 (true)
Manufacturer’s JEDEC ID Code 64-71 7Fh, 7Fh,
7Fh, 7Fh,
B0h
OCZ
Module Part Number 73-90 - OCZ2N900SR1G
Module Manufacturing Date 93-94 00h, 00h Not defined
Module Serial Number 95-98 00h, 00h,
00h, 00h
Not defined

Supported CAS# latencies — 5, 4, and 3. But cycle times are specified only for the first two values: main (CL X = 5) and reduced (CL X-1 = 4). The first value (CL X = 5) corresponds to the cycle time of 2.5 ns (400 MHz), i.e. DDR2-800. Timings for this case can be written with noninteger values as 5-5-5-14.8. They will be most likely rounded up to 5-5-5-15. The second value (CL X-1 = 4) corresponds to the slightly outdated DDR2-533 mode (3.75 ns cycle time, 266.7 MHz) with noninteger 4-3.33-3.33-9.87 timings, which can be rounded up to 4-4-4-10. As we have already noted above, CAS# latency reduced by two (CL X-2 = 3) does not correspond to any sensible operating mode, which is definitely a mistake.

Manufacturer's JEDEC ID Code and Part Number of the module are correct. But there is no information about its manufacturing date and serial number. These modules also support EPP, so let's analyze information from this part of SPD.

Parameter Byte(s) (bits) Value Expansion
EPP Identifier String
99-101
4E566Dh
EPP SPD Support
EPP Profile Type Identifier
102
B1h
Full Profiles
Profile for Optimal Performance
103 (1:0)
01h
Profile 1
Enabled Profiles
103 (7:4)
03h
Profile 0: available
Profile 1: available
Profile 0
Voltage Level
104 (6:0)
14h
2.3 V
Addr CMD rate
104 (7)
01h
2T
Cycle time (tCK)
109
22h
2.20 ns (454.5 MHz)
CAS# latency (tCL)
110
10h
4
Minimum RAS to CAS delay (tRCD)
111
23h
8.75 ns (3.98)
Minimum Row Precharge Time (tRP)
112
19h
6.25 ns (2.84)
Minimum Active to Precharge Time (tRAS)
113
21h
33.0 ns (15.00)
Write recovery time (tWR)
114
28h
10.0 ns (4.55)
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC)
115
32h
50.0 ns (22.73)
Profile 1
Voltage Level
116 (6:0)
14h
2.3 V
Addr CMD rate
117 (7)
01h
2T
Cycle time (tCK)
121
22h
2.20 ns (454.5 MHz)
CAS# latency (tCL)
122
10h
4
Minimum RAS to CAS delay (tRCD)
123
21h
8.25 ns (3.75)
Minimum Row Precharge Time (tRP)
124
19h
6.25 ns (2.84)
Minimum Active to Precharge Time (tRAS)
125
1Fh
31.00 ns (14.09)
Write recovery time (tWR)
126
30h
12.00 ns (5.45)
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC)
127
2Ch
44.00 ns (20.00)

EPP data look very interesting. Unlike the above OCZ DDR2 PC2-6400 modules with abbreviated EPP profiles, the OCZ DDR2 PC2-7200 modules contain information about two full profiles (Profiles 0 and 1). Both of them are valid, but they correspond... to almost identical operating modes(!), there are only minor differences. Namely, both profiles set memory modules to DDR2-900 (approximately 454.5 MHz, 2.2 ns cycle time) at 2.3 V (complies with manufacturer's specifications) and 2T address command rate. Only main memory timings differ a little. In the first case they look like 4-3.98-2.84-15 (rounded up to 4-4-3-15). The second case - 4-3.75-2.84-14.09. When rounded up, we also get 4-4-3-15 (matches the official scheme), but EPP profiles also differ in other timings like tWR and tRC. Anyway, Profile 1 is considered optimal.

SPD data in the OCZ DDR2 PC2-7200 modules (including the EPP extensions) evidently differ from SPD (and EPP) data in the OCZ DDR2 PC2-6400 modules reviewed above. This way or another, there are some inaccuracies or even mistakes in both cases. Thus, OCZ's approach to programming SPD is quite original, if not slipshod. In conclusion let's examine SPD in our last contender — OCZ DDR2 PC2-8000. These modules do not support EPP, so SPD contains only the "standard" section.

OCZ DDR2 PC2-8000

Parameter Byte Value Expansion
Fundamental Memory Type 2 08h DDR2 SDRAM
Number of Row Addresses on this assembly 3 0Eh 14 (RA0-RA13)
Number of Column Addresses on this assembly 4 0Ah 10 (CA0-CA9)
Number of DIMM Banks 5 61h 2 physical banks
Data Width of this assembly 6 40h 64 bit
Voltage Level 8 05h SSTL 1.8V
SDRAM Cycle time (tCK) at maximum supported CAS# latency (CL X) 9 25h 2.50 ns (400.0 MHz)
DIMM configuration type 11 00h Non-ECC
Refresh Rate/Type 12 82h 7.8125 ms — 0.5x reduced self-refresh
Primary SDRAM Width (organization type) of the memory module chips 13 08h x8
Error Checking SDRAM Width (organization type) of the memory chips in the ECC module 14 00h Not defined
Burst Lengths Supported (BL) 16 0Ch BL = 4, 8
Number of Banks on SDRAM Device 17 04h 4
CAS Latency (CL) 18 38h CL = 5, 4, 3
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-1) 23 30h 3.00 ns (333.3 MHz)
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-2) 25 37h 3.70 ns (270.3 MHz)
Minimum Row Precharge Time (tRP) 27 32h 12.5 ns
5.00, CL = 5
4.17, CL = 4
3.37, CL = 3
Minimum Row Active to Row Active delay (tRRD) 28 28h 10.0 ns
4.00, CL = 5
3.33, CL = 4
2.70, CL = 3
Minimum RAS to CAS delay (tRCD) 29 32h 12.5 ns
5.00, CL = 5
4.17, CL = 4
3.37, CL = 3
Minimum Active to Precharge Time (tRAS) 30 25h 37.0 ns
14.80, CL = 5
12.33, CL = 4
10.00, CL = 3
Module Bank Density 31 80h 512 MB
Write recovery time (tWR) 36 3Ch 15.0 ns
6.00, CL = 5
5.00, CL = 4
4.05, CL = 3
Internal write to read command delay (tWTR) 37 1Eh 7.5 ns
3.00, CL = 5
2.50, CL = 4
2.02, CL = 3
Internal read to precharge command delay (tRTP) 38 1Eh 7.5 ns
3.00, CL = 5
2.50, CL = 4
2.02, CL = 3
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 41, 40 36h, 00h 54.0 ns
21.60, CL = 5
18.00, CL = 4
14.59, CL = 3
SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) 42, 40 69h, 00h 105.0 ns
42.00, CL = 5
35.00, CL = 4
28.38, CL = 3
Maximum device cycle time (tCKmax) 43 80h 8.0 ns
SPD Revision 62 12h Revision 1.2
Checksum for Bytes 0-62 63 DAh 218 (true)
Manufacturer’s JEDEC ID Code 64-71 7Fh, 7Fh,
7Fh, 7Fh,
B0h
OCZ
Module Part Number 73-90 - OCZ2TA1000VX21G
Module Manufacturing Date 93-94 00h, 00h Not defined
Module Serial Number 95-98 00h, 00h,
00h, 00h
Not defined

SPD data in these modules are similar to those in the first product we reviewed today — OCZ DDR2 PC2-6400. Supported CAS# latencies are 5, 4, and 3. The first value (CL X = 5) corresponds to the cycle time of 2.5 ns (400 MHz), i.e. DDR2-800. Timings for this case are written as 5-5-5-14.8 (5-5-5-15). Reduced CAS# latency (CL X-1 = 4) corresponds to DDR2-667 (3.0 ns cycle time, 333.3 MHz) with 4-4.17-4.17-12.33 (4-5-5-13) timings. And finally, CAS# latency reduced by two (CL X-2 = 3) corresponds to erroneous but wide-spread DDR2-533 with the cycle time of 3.7 ns (270.3 MHz). Timings for this case are written as 3-3.37-3.37-10.0 (3-4-4-10).

Manufacturer's JEDEC ID Code and Part Number of the modules are correct; but there is no information about their manufacturing date and serial numbers.

Testbed configuration

Testbed 1

  • CPU: AMD Athlon 64 X2 4800+ (Socket AM2), nominal frequency - 2.4 GHz (200 x12)
  • Chipset: NVIDIA nForce 590 SLI
  • Motherboard: ASUS CROSSHAIR, BIOS 0502 dated 01/02/2007

Test results

The OCZ modules were tested on the AMD platform (Athlon 64 X2 4800+) based on the ASUS CROSSHAIR motherboard (Testbed 1) that supports EPP. The modules were tested in two modes in all cases:

1. Nominal: standard CPU frequency, 400 MHz memory (DDR2-800), standard memory settings (by SPD), EPP data are not used.

2. Optimal, corresponds to the optimal EPP profile, allows to overclock a processor (up to 15%) to get maximum recommended memory frequency. We configured CPU and memory frequencies manually in case of OCZ DDR2 PC2-8000 modules, which do not support EPP.

OCZ DDR2 PC2-6400

Parameter Testbed 1
CPU clock, MHz
(FSB clock x FID)
2400
(200x12)
2400
(200x12)
Memory frequency, MHz
(DDR2 MHz)
400
(800)
400
(800)
Default memory timings, voltage
5-5-5-15-2T,
1.8 V
4-4-4-15-1T,
2.0 — 2.3 V
Minimal memory timings, voltage
4-4-3-2T,
2.2 V
-
Average memory read bandwidth (GB/sec),
1 core
3.94
(4.06)
-
Average memory write bandwidth (GB/sec),
1 core
3.27
(3.10)
-
Max. memory read bandwidth (GB/sec),
1 core
7.84
(7.99)
-
Max. memory write bandwidth (GB/sec),
1 core
6.94
(6.93)
-
Average memory read bandwidth (GB/sec),
2 cores
6.65
(6.98)
-
Average memory write bandwidth (GB/sec),
2 cores
3.96
(4.05)
-
Max. memory read bandwidth (GB/sec),
2 cores
8.65
(9.33)
-
Max. memory write bandwidth (GB/sec),
2 cores
6.46
(6.61)
-
Minimum pseudo-random access latency (ns)
28.1
(26.7)
-
Minimum random access latency* (ns)
80.7
(78.4)
-

*32 MB block size

Let's start with test results of OCZ DDR2 PC2-6400 memory modules. They officially support DDR2-800 mode with 4-4-4-15 timings, and most importantly, 1T address command rate. As you can see on the table above, BIOS sets memory timings for these modules to 5-5-5-15-2T by default. Their performance is on the typical DDR2-800 level for this CPU frequency (2.4 GHz). Memory voltage raised to 2.2 V, timings can be reduced to 4-4-3 (like most other DDR2 models, these modules are not sensitive to changes of the last standard timing - tRAS), but the address command rate must still be 2T. Attempts to use hardcore timings 4-3-3-2T as well as 1T mode with any timings resulted in memory system errors.

Thus, OCZ DDR2 PC2-6400, modules, designed for DDR2-800 4-4-4-15-1T, cannot operate in this mode. The EPP profile failed to save the day (no wonder, EPP data in these modules are represented by a single abbreviated profile, which does not allow to tweak additional timings and voltages), even when we tried to raise voltage to 2.3 V.

OCZ DDR2 PC2-7200

Parameter Testbed 1
CPU clock, MHz
(FSB clock x FID)
2400
(200x12)
2736
(228x12)
Memory frequency, MHz
(DDR2 MHz)
400
(800)
456
(912)
Default memory timings, voltage
5-5-5-15-2T,
1.8 V
4-4-3-15-2T,
2.2 V
Minimal memory timings, voltage
4-3-3-1T,
2.3 V
-
Average memory read bandwidth (GB/sec),
1 core
3.94
(4.12)
4.56
Average memory write bandwidth (GB/sec),
1 core
3.30
(3.42)
3.84
Max. memory read bandwidth (GB/sec),
1 core
7.83
(8.13)
9.04
Max. memory write bandwidth (GB/sec),
1 core
6.94
(6.79)
7.88
Average memory read bandwidth (GB/sec),
2 cores
6.65
(7.14)
7.79
Average memory write bandwidth (GB/sec),
2 cores
3.93
(4.51)
4.82
Max. memory read bandwidth (GB/sec),
2 cores
8.69
(9.82)
10.26
Max. memory write bandwidth (GB/sec),
2 cores
6.46
(6.69)
7.52
Minimum pseudo-random access latency (ns)
28.1
(25.7)
23.9
Minimum random access latency* (ns)
80.2
(78.3)
67.9

*32 MB block size

When the OCZ DDR2 PC2-7200 modules operated in the standard DDR2-800 mode, our ASUS CROSSHAIR motherboard set timings to 5-5-5-15-2T (like in the previous case). Performance of PC2-7200 modules in this mode is similar to that of PC2-6400 modules reviewed above. But the most interesting fact is that when memory voltage is raised (to 2.3 V), these modules can set 4-4-3 timings at the 1T address command rate. That's their biggest difference from the PC2-6400 modules reviewed above, which officially(!) work in 1T mode. Moreover, we managed to run these modules with 3-3-3-1T timings, but they resulted in errors.

The optimal EPP profile sets FSB clock to 228 MHz, which corresponds to 228x2 = 456 MHz memory bus frequency ("DDR2-912", a tad higher than the nominal "DDR2-900" mode) with 2.74 GHz CPU clock (CPU voltage was manually increased to 1.5 V for the sake of stability). In this case the timings were set to 4-4-3-15-2T, matching the manufacturer's scheme. The memory modules under review can still operate in this mode, but further reduction of timings (except for the ignored tRAS) as well as of the address command rate to 1T resulted in memory instability.

OCZ DDR2 PC2-8000

Parameter Testbed 1
CPU clock, MHz
(FSB clock x FID)
2400
(200x12)
2500
(250x10)
Memory frequency, MHz
(DDR2 MHz)
400
(800)
500
(1000)
Default memory timings, voltage
5-5-5-15-2T,
1.8 V
5-5-5-15-2T,
2.3 V
Minimal memory timings, voltage
4-3-3-1T,
2.3 V
4-4-4-2T,
2.3 V
Average memory read bandwidth (GB/sec),
1 core
3.90
(4.13)
4.35
(4.48)
Average memory write bandwidth (GB/sec),
1 core
3.28
(3.33)
3.61
(3.75)
Max. memory read bandwidth (GB/sec),
1 core
7.79
(8.13)
8.40
(8.50)
Max. memory write bandwidth (GB/sec),
1 core
6.94
(6.79)
7.19
(7.21)
Average memory read bandwidth (GB/sec),
2 cores
6.60
(7.14)
7.52
(7.79)
Average memory write bandwidth (GB/sec),
2 cores
4.08
(4.46)
4.70
(5.11)
Max. memory read bandwidth (GB/sec),
2 cores
8.61
(9.82)
10.37
(11.01)
Max. memory write bandwidth (GB/sec),
2 cores
6.48
(6.70)
6.92
(7.04)
Minimum pseudo-random access latency, ns
28.6
(25.7)
24.5
(23.2)
Minimum random access latency*, ns
80.6
(78.4)
72.1
(67.8)

*32 MB block size

When we used OCZ DDR2 PC2-8000 modules in the official DDR2-800 mode, the ASUS CROSSHAIR motherboard set 5-5-5-15-2T timings by default. As in case with PC2-7200 modules (not PC2-6400), raising memory voltage to 2.3 V allows to reduce timings to 4-3-3 (further reduction to 3-3-3 results in errors) and address command rate to 1T. Performance results of PC2-8000 and PC2-7200 modules are practically identical in this case.

As the OCZ DDR2 PC2-8000 modules do not support EPP, we set the "DDR2-1000" mode manually by increasing the system bus frequency to 250 MHz to get 500 MHz memory and 2.5 GHz CPU (250x10). Minimal timings under these conditions are 4-4-4-2T at 2.3 V. This result matches the official values (an attempt to set lower timings immediately resulted in memory failures).

Bottom line

Tested samples of high-speed memory modules from OCZ (PC2-6400, PC2-7200, and PC2-8000) produce an ambiguous impression. The most unpleasant impression is produced by the careless approach of the manufacturer to programming SPD data (EPP in particular), which can have an immediate effect on compatibility of memory modules with various motherboards. Moreover, the first of the samples reviewed (PC2-6400) couldn't operate in the standard officially supported mode at 1T address command rate (at least on the ASUS CROSSHAIR motherboard). What concerns goodies, the other two representatives (PC2-7200 SLI-Ready Edition and PC2-8000 Titanium Alpha VX2) can operate in the standard DDR2-800 mode with "extreme" 4-3-3 timings and 1T address command rate. This is not quite typical of most 2 GB dual-channel memory kits for AMD AM2. At the same time, memory modules of these series seem to be overclocked to the limit in unofficial modes ("DDR2-900" and "DDR2-1000", correspondingly), because it's impossible to reduce timings as well as the address command rate (to 1T) any further. But stable operation of PC2-7200/PC2-8000 modules in the fastest modes is an advantage of these OCZ series, considering the problem with PC2-6400 modules.



Dmitri Besedin (dmitri_b@ixbt.com)
March 26, 2007


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