We proceed with the analysis of the most important characteristics of high-performance DDR2 memory modules using our RightMark Memory Analyzer. Today we are going to review a new interesting solution from Kingston (considering the new tendency to raise memory capacity for operating systems and applications) — a dual-channel kit of DDR2-800 high-end HyperX memory modules (4 GB in total) with relatively low latencies (4-4-4-12-2T).
Manufacturer Information
Module manufacturer: Kingston Technology
Manufacturer of module chips: unknown
Web site of the module manufacturer: http://www.kingston.com/hyperx/products/khx_ddr2.asp
Module Exterior
Module Part Number
The manufacturer's web site does not publish the DDR2 Part Number expansion. Datasheet on the modules with Part Number KHX6400D2LLK2/4G runs that this product is a kit of two modules with low latencies (Low Latency, "LL"), 2 GB each, 256M × 64 configuration, based on sixteen 128M x8 chips. The manufacturer guarantees stable operation of the modules in DDR2-800 mode with 4-4-4-12 timings at relatively low 1.9 V. But the default mode in the SPD chip is DDR2-667 with 5-5-5-15 timings at 1.8 V.
SPD chip data
Description of the general SPD standard:
Description of the specific SPD standard for DDR2:
| Parameter |
Byte |
Value |
Expansion |
| Fundamental Memory Type |
2 |
08h |
DDR2 SDRAM |
| Number of Row Addresses on this assembly |
3 |
0Eh |
14 (RA0-RA13) |
| Number of Column Addresses on this assembly |
4 |
0Ah |
10 (CA0-CA9) |
| Number of DIMM Banks |
5 |
61h |
2 physical banks |
| Data Width of this assembly |
6 |
40h |
64 bit |
| Voltage Level |
8 |
05h |
SSTL 1.8V |
| SDRAM Cycle time (tCK) at maximum supported CAS# latency (CL X) |
9 |
30h |
3.00 ns (333.3 MHz) |
| DIMM configuration type |
11 |
00h |
Non-ECC |
| Refresh Rate/Type |
12 |
82h |
7.8125 ms — 0.5x reduced self-refresh |
| Primary SDRAM Width (organization type) of the memory module chips |
13 |
08h |
x8 |
| Error Checking SDRAM Width (organization type) of the memory chips in the ECC module |
14 |
00h |
Not defined |
| Burst Lengths Supported (BL) |
16 |
0Ch |
BL = 4, 8 |
| Number of Banks on SDRAM Device |
17 |
08h |
8 |
| CAS Latency (CL) |
18 |
38h |
CL = 5, 4, 3 |
| Minimum clock cycle (tCK) at reduced CAS# latency (CL X-1) |
23 |
3Dh |
3.75 ns (266.7 MHz) |
| Minimum clock cycle (tCK) at reduced CAS# latency (CL X-2) |
25 |
50h |
5.00 ns (200.0 MHz) |
| Minimum Row Precharge Time (tRP) |
27 |
3Ch |
15.0 ns
5, CL = 5
4, CL = 4
3, CL = 3 |
| Minimum Row Active to Row Active delay (tRRD) |
28 |
1Eh |
7.5 ns
2.5, CL = 5
2.0, CL = 4
1.5, CL = 3 |
| Minimum RAS to CAS delay (tRCD) |
29 |
3Ch |
15.0 ns
5, CL = 5
4, CL = 4
3, CL = 3 |
| Minimum Active to Precharge Time (tRAS) |
30 |
2Dh |
45.0 ns
15, CL = 5
12, CL = 4
9, CL = 3 |
| Module Bank Density |
31 |
01h |
1024 MB |
| Write recovery time (tWR) |
36 |
3Ch |
15.0 ns
5, CL = 5
4, CL = 4
3, CL = 3 |
| Internal write to read command delay (tWTR) |
37 |
1Eh |
7.5 ns
2.5, CL = 5
2.0, CL = 4
1.5, CL = 3 |
| Internal read to precharge command delay (tRTP) |
38 |
1Eh |
7.5 ns
2.5, CL = 5
2.0, CL = 4
1.5, CL = 3 |
| SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) |
41, 40 |
3Ch, 06h |
60.0 ns
20, CL = 5
16, CL = 4
12, CL = 3 |
| SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) |
42, 40 |
7Fh, 06h |
127.5 ns
42.5, CL = 5
34.0, CL = 4
25.5, CL = 3 |
| Maximum device cycle time (tCKmax) |
43 |
80h |
8.0 ns |
| SPD Revision |
62 |
12h |
Revision 1.2 |
| Checksum for Bytes 0-62 |
63 |
13h |
19 (true) |
| Manufacturer’s JEDEC ID Code |
64-71 |
7Fh, 98h |
Kingston |
| Module Part Number |
73-90 |
- |
2G-UDIMM |
| Module Manufacturing Date |
93-94 |
07h, 02h |
Year 2007, Week 2 |
| Module Serial Number |
95-98 |
66h, 26h,
BEh, 72h |
72BE2666h |
SPD contents look quite standard. All three CAS latencies are supported — 5, 4, and 3. The first value (CL X = 5) corresponds to DDR2-667 (3.0 ns cycle time, 333.3 MHz) with 5-5-5-15 timings (sharp), which matches the official values, specified in the documentation. The second CAS latency value (CL X-1 = 4) corresponds to DDR2-533 (3.75 ns cycle time, 266.7 MHz) with 4-4-4-12 timings. And finally, the last CAS latency value (CL X-2 = 3) corresponds to DDR2-400 with integer 3-3-3-9 timings.
What concerns SPD peculiarities, we can mention a very high (that's probably the first time we have seen it in a DDR2 memory module) tRFC value (127.5 ns). To all appearances, it has to do with using memory chips with 8 logical banks (most DDR2 chips typically use 4 logical banks) to reach high memory capacity (2 physical banks, 1024 MB each).
SPD revision number, manufacturer's JEDEC ID Code, manufacturing date, and serial number of the module are specified correctly. Information about Part Number of the module is available ("2G-UDIMM"), but it does not match the Part Number printed on the modules (KHX6400D2LLK2/4G).
These modules do not support SPD extensions of the EPP standard.
Testbed configuration
Testbed 1
- CPU: AMD Athlon 64 X2 4800+ (Socket AM2), 2.4 GHz (200 x12)
- Chipset: NVIDIA nForce 590 SLI
- Motherboard: ASUS CROSSHAIR, BIOS 0502 dated 01/02/2007
Test results
The modules were tested on the AMD platform (Athlon 64 X2 4800+) based on the ASUS CROSSHAIR motherboard (Testbed 1). The modules were tested in two modes: "by default" (automatic memory configuration by SPD) and in the "optimal" mode (memory was configured manually by manufacturer's recommendations).
| Parameter |
Testbed 1 |
CPU clock, MHz
(FSB clock x FID) |
2400
(200x12)
|
2400
(200x12)
|
Memory frequency, MHz
(DDR2 MHz) |
300
(600)
|
400
(800)
|
| Default memory timings,
voltage |
5-5-5-15-2T,
1.8 V
|
4-4-4-12-2T,
1.9 V
|
| Minimal memory timings,
voltage |
(not tested)
|
ditto,
up to 2.3 V
|
Average memory read bandwidth
(GB/sec),
1 core |
3.44
|
4.08
|
Average memory write bandwidth
(GB/sec),
1 core |
2.26
|
2.92
|
Max. memory read bandwidth
(GB/sec),
1 core |
6.98
|
8.04
|
Max. memory write bandwidth
(GB/sec),
1 core |
6.91
|
6.92
|
Average memory read bandwidth
(GB/sec),
2 cores |
5.73
|
7.11
|
Average memory write bandwidth
(GB/sec),
2 cores |
2.83
|
3.86
|
Max. memory read bandwidth
(GB/sec),
2 cores |
6.92
|
9.47
|
Max. memory write bandwidth
(GB/sec),
2 cores |
6.55
|
6.80
|
| Minimum pseudo-random
access latency, ns |
33.5
|
26.4
|
| Minimum random access
latency*, ns |
85.0
|
66.7
|
*32 MB block size
In the first case, memory frequency was 300 MHz ("DDR2-600") owing to limitations of the CPU memory controller (integer frequency divider, in this case it was 2400/8 = 300 MHz). Timings, set by BIOS automatically, match SPD values - 5-5-5-15-2T. Memory demonstrates mediocre performance in this mode, which is a typical situation for AMD AM2 processors at low memory frequencies.
These modules are stable in DDR2-800 mode with 4-4-4-12(-2T) timings, recommended by the manufacturer, and at a minimal voltage increase to 1.9 V. At the same time, the recommended timings turned out to be the lowest possible values — any attempts to set lower timings (except for tRAS, which value is usually ignored by the memory system) resulted in immediate failures, even when memory voltage was raised to 2.3 V. Memory demonstrates very high performance in this case, despite its large volume.
Bottom line
Kingston HyperX DDR2-800 KHX6400D2LLK2/4G memory modules with high capacity and low latencies proved to be reliable in conditions recommended by the manufacturer (DDR2-800, 1.9 V, 4-4-4-12-2T). That's our first review of the offer in the new category of memory modules (4 GB in total), which can operate in such a fast mode at only slightly raised voltage. Although we failed to reduce timings any further (even when we raised memory voltage), this product is a great achievement of Kingston and DDR2 memory industry in general.
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