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Little Princes PXA

November 6, 2003



Modern PDAs and smartphones have very strict requirements for the elemental base - you can come across models which are 1 cm thick and weigh 100 g in spite of their iron case, capacious batteries and a big screen. Looking at my HP iPaq 1910 I wonder whether there's a board with a processor, memory and other logical elements at all: 

How did they fit it in there? 

Such miniature dimensions are possible due to the compact systems which house not only the CPU core but also many other controllers such as controllers of an LCD screen, power supply and core clock management, USB, audio interface, interfaces of memory cards of various standards and general I/O interfaces (for buttons, wheels and joysticks). The chip also integrates a controller of various system memory types, both random-access and Flash. The latest solutions are even more integrated: the chip based system also contains one or two Flash dies for OS and other software. Soon it will also integrate RAM of the industry standard size: 32, 64 and 128 MB. 

Today we'll get into the history, look at the prospects and the current situation of the most popular chip based systems - Intel's PXA products based on XScale's RISC core. 

A bit of history

The Intel XScale RISC originates from a very successful solution from Advanced RISC Machines Ltd (of the RISC architecture named ARM) and is the extension of this architecture being backward compatible in software. ARM was founded in 1990 by Acron, Apple (sic!) and VLSI. Acron wanted a CPU for its Archimedus PC, which had a successful architecture but failed to become popular. Apple looked for a RISC architecture to replace MACs based on the Motorolla 68k CISC architecture, and VLSI planned to make processors based on this architecture to use it in various integrated and flexible systems. 

The architecture turned out to be a success: various ARM core versions (especially 6,7,9,10,11) and various finished solutions were licensed for a wide range of companies including DEC, Intel, TI, Atmel etc. The solutions had low power consumption (relative to the performance) and flexible adaptation for specific needs including additional instructions sets for signal processing (multimedia) or effective implementation of Java byte code. 

Here are some of ARM solutions:




Here you can find details on the basic architecture, instructions and other aspects of original ARMs. 

This simple and easily adaptable architecture pressed out its competitors from the PDA market (other popular RISC architectures NEC VR and MIPS) and the Motorolla DragonBall that descends from single-chip Motorolla 68 microcomputers. At the moment the ARM architecture and its derivatives serve a base for most chip based mobile solutions from various manufacturers (not only from Intel, but also from Atmel and Texas Instruments, like OMAP and others). 

Three most popular (in such devices) mobile OS core - Windows CE, Symbian and PalmOS - have been developing within the frames of this architecture. Linux solutions which are much less popular are also ported to the ARM. This architecture reigns on the market of PDAs, smartphones and other smart mobile solutions. The periods of domination of this architecture (in one or another Hi-tech sphere) alternate with the periods of competition of several architectures. In different spheres such alternation has different speeds and time of "monarchy and democracy". x86 architectures have been reigning on the PC market for a long time already (except for the PowerPC in Apple's products). I think that the ARM's domination in some or others forms on the market of PDAs and smartphones won't end soon. The matter is that what PDA designers prefer doesn't depend on development of the architecture - the computational power is important but it isn't determining. Simplicity, low power consumption, flexibility, software and development tools are the most important, and the ARM architecture has no problems with it. A lot also depends on how the system is realized on the chip, what controllers and subsystems are integrated, what memory types and size are supported, how much power is consumed etc. But all such aspects develop independently from the core architecture. By the way, in a modern system of such class the core takes less than half of a die, the other part is taken for controllers and other service systems. 

A bit after the announcement of the ARM, DEC licensed the ARM architecture and instruction set and developed their own advanced version of the core named StrongARM. When DEC merged with Compaq, the StrongARM core was purchased by Intel, and then for a long time it served a base for SA1110 based systems for Windows CE PDAs. The integration degree in such systems was lower compared to modern solutions, and many functions were on the shoulders of the second chip-companion. They had a dated serial interface and some other features which are not used anymore.

Then Intel developed its own core and architecture version compatible with the ARM v5 in instructions - Xscale. The new core consumes less power and scales better as the core clock grows up - 400MHz solutions are already available and 600/800MHz versions based on the Xscale are expected soon. Besides, the new architecture supports instructions that deliver effective communication with various coprocessors based on the same chip. One of the main extensions is the Wireless MMX, a 64bit SIMD instruction set and a SIMD coprocessor which will be integrated into new XScale based chips. These instructions effectively process video, 3D graphics, sound and other elements traditional of SIMD. Although this set is not compatible with the SSE/SSE2 of Intel's desktop solutions, it has very similar features, that is why algorithms are not needed to be rewritten, vector commands can be translated without any changes in many cases, only the precision and data representation must be controlled. 

For effective utilization of software on Xscale based systems they should be recompiled with an adequate optimizing compiler to let the performance grow twice. In this respect the situation reminds the release of the Pentium - software compilation was oriented towards the 486 processors and the programs ran not very efficiently, but later, with appropriate compilers the performance grew up considerably. 

Family

So, the Xscale core is used for all Intel's systems produced for PDAs, smartphones and other mobile applications. 

Intel PXA255

  • 32bit Xscale RISC core, ARM v.5TE compatible instructions
  • 200, 300, 400 MHz
  • 0.18-micron technology 
  • superscalar execution
  • special 40bit accumulator and 16bit SIMD instructions for video and audio processing taken from DSP architectures (do not confuse with Wireless MMX) 
  • high-speed interface for synchronous Intel Strata Flash memory 
  • increased performance and low power consumption modes
  • 32 KB cache for instructions and 32 KB cache for data
  • special 2 KB cache for stream multimedia data
  • memory controller: 4 banks, 100MHz, support for 2.5 and 3.3V SDRAM, SRAM, ROM, Flash ROM etc., 16 and 32bit bus width. Up to 256 MB RAM for all 4 RAM banks.
  • dual-channel PCMCIA and Compact Flash controller for peripherals and memory cards
  • MMC/SD memory card controller
  • 15 single-bit general purpose I/O ports with interruption support
  • integrated programmable clock frequency synthesizer  and timer
  • 16 DMA channels
  • LCD display controller with hardware acceleration of filling and transition of rectangular units (active and passive matrices, 1- and 2-page, up to 16 bits per pixel).
  • AC97
  • USB (ultimate interface, not host)
  • UART (one crippled, for internal device, and one with full hardware transmission control)
  • IrDA interface
  • Bluetooth (standard serial 960 Kbit UART interface to transmit-receive module) 
  • I2C and I2S buses
  • SSP interface
  • 256 pin PBGA case, 17x17 mm
  • wide allowable temperature range.




This is a block diagram of the PXA256. The configurable memory controller on the right also executes functions of the CF/PCMCIA interface. Up to 6 banks can be configured, each can be CF/PCMCIA, RAM or ROM, with different parameters and memory bandwidth. 

The left part is provided for controllers of various devices, some of them have a direct access to data, via a DMA channel, taking them from the system memory. Here are they:

  • Clock
  • OS precise timer 
  • Two pulse-width modulation generators
  • Interrupt controller
  • Clock frequency synthesizer and power management controller
  • All interfaces listed above.

The system also contains the display controller supporting 1,2,4,8 and 16 bit color (up to 8 bits per color and 16 bit palette), active and passive matrixes supported, with one or two pages. The maximum pixel frequency is 83 MHz. For example, for the display of 800x600 at the refresh rate of 75 Hz the pixel frequency must be 36 MHz. The maximum resolution supported is 1024x1024. The quality hardware 16-bit dithering is realized for passive panels.

Intel PXA26X

The main advantage and distinguishing feature of this model is the Flash memory integrated into the same package. Such integration degree makes this solution attractive for smartphones and usual cell phones with advanced functions. Here's the cross section of this chip based system:




One processor die and one or two Flash memory dies. Besides, the new series has more peripheral controllers. So: 

  • 32 bit Xscale RISC core, instructions compatible with ARM v.5TE 
  • PXA261 200 MHz, PXA262 200, 300 MHz
  • 0.18 technology
  • PXA261 16 MB, PXA262 32 MB of integrated Flash memory
  • superscalar execution 
  • special 40bit accumulator and 16bit SIMD instructions for video and audio processing taken from DSP architectures (do not confuse with Wireless MMX) 
  • high-speed interface for synchronous Intel Strata Flash memory. 
  • increased performance and low power consumption modes.
  • 32 KB cache for instructions and 32 KB cache for data
  • special 2 KB cache for stream multimedia data
  • memory controller: 4 banks, 100MHz, support for 2.5 and 3.3V SDRAM, SRAM, ROM, Flash ROM etc., 16 and 32bit bus width. 
  • dual-channel PCMCIA and Compact Flash controller for periherals and memory cards
  • MMC/SD memory card controller
  • 20 single-bit general purpose I/O ports with interruption support
  • integrated programmable clock frequency synthesizer  and timer
  • 16 DMA channels
  • LCD display controller with hardware acceleration of filling and transition of rectangular units (active and passive matrices, 1- and 2-page, up to 16 bits per pixel).
  • AC97
  • USB (ultimate interface, not host)
  • UART (one crippled, for internal devices, and one with full hardware transmission control)
  • IrDA interface
  • Bluetooth (standard serial 960 Kbit UART interface to transmit-receive module) 
  • I2C and I2S buses
  • SSP/NSSP/ASSP interfaces
  • 294 pin PBGA case, 14x14 (!) mm
  • wide allowable temperature range




So, the main difference between the block diagrams of the PXA26x and PXA255 is the synchronous Flash memory and additional controllers. The onboard Flash memory takes one of 6 banks, and the solution with the 256MB DRAM will have only one free bank for the CF/PCMCIA slot or other equipment of this kind (so called Variably Latency I/O Control). 

NSSP and ASSP indicate I/O interfaces meant for mobile (cellular ) applications - Network and Audio interfaces respectively.

Now let's see what's the use of such thick integration of functions and controllers in one chip. Here is how AC97 codecs are connected - one or even two:




And this is the display connection scheme:




And this scheme is for the MMC memory card connector (they couldn't avoid using several resistors):




About 90% of devices and schemes of a modern PDA or smartphone connect directly to its heart, the chip based system, without any intermediaries or unnecessary components. This is what the high system integration degree means. 

Future

What should we wait from such systems in future (in chronological order)? 

  • Clock rate - 600 and 800 MHz
  • Wireless MMX vector coprocessor
  • Up to 64 MB of integrated Flash memory 
  • Up to 256 MB of integrated SDRAM
  • Integrated wireless transceiver (WiFi/Bluetooth)
  • Integrated sampling and audio reproduction means
  • Integrated graphics coprocessor
  • Integrated cellular (or universal) transceiver

The integration degree is growing up. Why to solder unnecessary chips to the board? An ideal system must remind my old digital organizer, i.e. a board with one chip, battery, screen and pins for buttons. And what about connectors? Are they really needed in the epoch of wireless peripheral interfaces? All in chip... 

The only connector you have to bear is the power supply one. ;-)
 

Alexander Medvedev (unclesam@ixbt.com)

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