DDR2 vs DDR. Test Results in the Single-channel Mode
|
This is a small addition to our previous test results
which revealed a rather dubious advantage of DDR2 over DDR. It is
aimed at showing DDR2 in action, namely — at reaching the values
of real bandwidth that would be as close as possible to those mentioned
in the specs. To achieve that, we have to compare DDR2-533 and DDR-400
in the single-channel access mode where theoretical
bandwidth of both memory types (4.3 and 3.2 GB/s, respectively) is
lower than the peak one of the CPU bus (6.4 GB/s). And that is exactly
what we are going to do now.
Testbed configurations and software
Testbed 1
- CPU: Intel Pentium 4 3.4 GHz (Prescott core, Socket 478, FSB 800/HT, 1 MB L2)
- Mainboard: ASUS P4C800 Deluxe on Intel 875P
- Memory: 1x512 MMB PC3200 DDR SDRAM DIMM TwinMOS (timings: 2.5-3-3-6)
Testbed 2
- CPU: Intel Pentium 4 3.4 GHz (Prescott core, Socket 775, FSB 800/HT, 1 MB L2)
- Mainboard: ECS PF4 on Intel 915
- Memory: 1x512 MB PC2-4300 DDR2 SDRAM DIMM Samsung (timings: 4-4-4-8)
Software
Maximal real memory bandwidth
We measured maximal real memory bandwidth with the help of the Memory Bandwidth subtest, presets
Maximal RAM Bandwidth, Software Prefetch, MMX/SSE/SSE2, that use data prefetch from RAM to L2 CPU cache as the optimisation method. To optimise memory write in these tests, the Non-Temporal Store method is used, which enables to eliminate the influence of the CPU cache subsystem. To illustrate this, we're giving you the graph we have received on Prescott/DDR2 using SSE2 registers.
Prescott/DDR2, maximal real BW
But qualitative comparative characteristics are certainly much more interesting to look at.
| Memory type |
Maximal real BW, MB/s |
| Read (Software Prefetch) |
Write (Non-Temporal) |
| DDR-400 |
3290.1 |
3167.3 |
| DDR2-533 |
4287.2 |
4093.7 |
Well, we finally managed to get as close as possible to the announced BW value
of DDR2-533, the new memory type. Its real maximal BW was 4287.2 MB/s
in read operations (note that memory bus frequency was overstated
by 2-3 percent in both cases, which is clearly seen from DDR-400 test
results). We can say that it reached its peak value (which is, in
fact, 4266.7 MB/s = 533.3 MHz x 64 bits), even though the memory mode
was asynchronous. The efficiency of DDR2 write operations is somewhat
lower, but it's probably due to some microarchitectural peculiarities
of Prescott CPUs as we got almost the same value in our previous
tests carried out in the dual-channel mode.
Memory latency
The methodology we use to measure latency in the case of Pentium
4 CPUs was thoroughly developed, explained, and described before.
That is why we'll only mention it briefly: we use the pseudo-random
mode to read a quite large memory block (4 MB). The steps are 64 bytes
(a real size of Pentium 4 CPU L2 cache lines) and 128 bytes (the so-called
effective size related to hardware prefetch of the adjacent
line in all read modes).
To illustrate this, here's graphs of L2-RAM bus offload received on Prescott/DDR2 with a 128-byte step.
Prescott/DDR2, memory latency, 128-byte line size
Speaking about qualitative estimates, we should mention that latency values were invariably lower in the single-channel mode than in the dual-channel one.
However, it's no surprise as dual-channelness implies increased memory access latency (on the chipset level). And by the way, that is why memory latency values received in the single-channel mode should be considered the most correct ones (i.e. the closest ones to the original characteristics).
| Line size |
Memory type |
Pseudo-random read latency, ns |
| Minimal |
Medium* |
Maximal |
| 64 bytes |
DDR-400 |
28.0 |
31.4 |
31.6 |
| DDR2-533 |
29.3 |
30.5 |
34.8 |
| 128 bytes |
DDR-400 |
46.6 |
54.6 |
54.6 |
| DDR2-533 |
51.9 |
52.7 |
58.9 |
* no L2-RAM bus offload
It hardly makes any sense to compare "incorrect" and besides, very close values received at a 64-byte step. It is much more interesting to compare more objective ones received at 128 bytes. The results come as no surprise: DDR2 is clearly worse than DDR in what concerns latency. This time around, the difference is within 8-11 percent in favour of DDR (if we don't take into account the middle values, where there was no bus offload). It is a bit less than was in the dual-channel mode (15-16 percent), which means dual-channelness has more impact on DDR2 than DDR latency.
Conclusions
The results can hardly be called sensational. Maximal real bandwidth
of DDR2-533 memory really matches the announced 4.3 GB/s in the single-channel
mode and exceeds DDR-400 memory bandwidth in it. However, it can't
be referred to its indisputable advantages at least because current
Intel i915/i925
chipsets supporting DDR2 can also work perfectly in the dual-channel
mode. And that makes the single-channel DDR2 absolutely unattractive
compared to the same dual-channel DDR. Thus, the main previously-made
conclusion holds good: the use of DDR2 will not be appropriate at
least until the appearance of the first CPUs with bus frequency of
1067 MHz and higher. This will enable to overcome the restriction
imposed by CPU bus speed on real bandwidth of the memory subsystem
in the dual-channel mode.
Write a comment below. No registration needed!
|
|
 |
|
|
|
