iXBT Labs - Computer Hardware in Detail






October '2001 Hardware Digest

To say that October was a rapid month with a fountain of innovations is, probably, to say nothing. Despite numerous announced novelties technological news were the most important this month. So, let's start with them.


Still often we hear about 0,13 microns, 300 mm, copper, SOI, and other similar terms that mark a significant crisis in chip production, and in some degree leading us to a new era. Transition to new production engineering is both reduction of crystal dimensions, and, accordingly, increase of chip yield per plate (and especially in case of increasing plate sizes up to 300 mm), more economic chip operation, and, at last, raising prestige in customers opinion. No need to save money - is it a recession or not - let them faster transit to new technological norms. The largest part of R&D expenses of serious companies was aimed this year at namely the fastest transition to 0,13 micron technical process for mass production.

I shall mark that Intel became the first to achieve serious success in this direction - $7.5 billion of this year capital expenses were not a waste of money, and company still sticks to this level despite all profit problems. The past month was marked by the victorious official company's report about Fab 22 launch in Chandler, Arizona, USA - a first sign of Intel's factories initially aimed at 0,13 micron silicon plates manufacture. Here for the first time Intel is going to start the large-scale manufacture of PIII and P4 processors with new technical process norms. Still a little fly in the ointment: plates produced by Fab 22 constructed for record 18 months and costed Intel $2 billion, will nevertheless be 200mm, so an essential increase of chip yield is still doubtful. However next 0,13 micron technical process enterprises are at hand:

  • Fab 20 in Hillsboro: same 8-inch plates, 0,13 microns technical process, to produce Pentium III processors first then Northwood
  • D2 in Santa Clara: 8-inch plates, 0,18 - 0,13 micron technical process, basically to produce flash-memory
  • Fab 17 in Hudson: this factory bought already in 1998 from legendary Digital Equipment Corp. have been producing samples of 0,13 micron chips since September,
  • D1C In Hillsboro: the most interesting factory will work with 300 mm plates with 0,13 micron norms. The factory has been producing samples since March, however, mass chip production is not expected before New Year
  • Fab 11x in Rio-Rancho: same 0,13 micron technical process and 300 mm plates, mass production is actually expected closer to the end of 2002

Intel is followed by, first of all, TSMC, VIA's general contractor for manufacture of its processors and now also a leading processor manufacturer for Transmeta. The latest news from Sony and Fujitsu that announced sales of serial notebooks with 0,13 micron Crusoe TM5800 processors in November lead to idea that TSMC is very close to mass production of large chips of new 0,13 micron technical process.

It would, certainly, be desirable to mention something fixed about AMD, but how. Seems like company learned business management at medieval Japanese ministry of foreign relations - minimum of information outside whether good, or bad. Until official announcement of a new chip/chipset/technical process there's only total silence in the best traditions of iron curtain epoch. However, rare lucky beggars that wandered Dresden Fab 30 obscurely inform that AMD's 0,13 micron has stumbled into problems that will have a negative effect on launch of mass production of 0,13 micron processor with Throughbred core prepared to be released in the first quarter, and then the one with Appaloosa core. I shall remind that AMD's new technical process as a whole is a compilation of technologies of Motorola and IBM, for the sake of justice, yet have not started mass production of 0,13 micron chips.

Among basic tendencies of semiconductor industry I shall mark a sharp growth of official reports from many companies about prelaunch works at SiGe plates factories. One shouldn't forget behind official processor/flash reports that there's a very serious and mega/giga hertz industry of networking and wireless (including mobile) communications where clock rate is the most important and determines productivity of entire channel and as consequence - system productivity.

Expensive, but best suitable SiGe technical process is implemented for frequencies of 20 GHz - 50 GHz. It's not enough to develop a qualitative chip, it is also good to make its characteristics maximally available to speak about success in the whole. Fights are serious in this sector, but at the first sight not so evident for an average subscriber of the same mobile communications (he may think like: "I don't care about phone's transceiver or operator's equipment, but the screen is nice and buttons are colored"). The requirements to network processors, " power brokers" of modern infrastructure, are still higher and higher - higher throughput, higher productivity; and accordingly, higher clock rates.

More than half-dozen companies announced new network processors this month - Agere, AMCC, EZChip, IBM, Mindspeed, IDT, NetLogic, Silicon Access, but who will manufacture all this?

And many are willing to manufacture. Agere Systems, RF Micro Devices, IBM, Mitsubishi (all four are going to join efforts in developing a suitable technical process for mass production), Atmel, Micrel, AmberWave Systems, Sony, Motorola, Chartered, Vitesse, Conexant, as well as ubiquitous TSMC and others have already reported about SiGe process availability up to 50 GHz.

The essence is not in companies names. The tendency is clear: by the end of 2002 - beginning of 2003, network technologies will likely enter a qualitative new level allowing to speak about communication equipment of a new generation.

By the way, alternatives are enough even in this area: North American Inphi startup company, for example, has recently announced commercial manufacture chips for fibre-optical networks with the same 50 GHz threshold frequency, but on indium-phosphide, InP base.

Major was month's beginning, minor was its end, but became the activity apogee of this half-year Microprocessor Forum 2001 for processor manufacturers. You won't likely see the majority of novelties announced on MPF in the near future. However, industry development tendencies announced for MPF week will likely produce headlines for the next year and a half.


Events like MPF happen once a year, not counting Intel's "solo concerts" on IDF twice a year.

First of all, I'd like to mark Intel on MPF. Three key moments of representatives' statement were: progressing 3GIO architecture (see our article "Arapahoe and HyperTransport data trunks"), innovating server chip lines, and establishing mobile and PDA processors in the market.

"Ballyhoos" about new PCI 3GIO or Arapahoe standard actually took place in August - September on IDF. As a whole, this part of the statement was reduced to ascertaining the fact of 3GIO recognition by all industry leaders.

It was much more interesting to learn about changes in Intel's plans of releasing server processors. Another new name - Nocona -has appeared for the first time. It's a new 32-bit server chip for dual-processor highly efficient systems to appear in the market in 2003. With Nocona Intel will have 4 server processor lines in total by 2003: Nocona, Banias, Deerfield, and Madison.

Deerfield and Madison are successors of McKinley and Itanium. They will be 64-bit while Banias and Nocona - 32-bit. Banias processor worth a separate description as MPF brought the very first details about it.

A remarkable fact was Banias to be based on P6 architecture, being gradually removed from other Intel's product lines. The basis of Banias's architecture is actually Pentium Pro that debuted in 1996 and some additional innovations for lower energy consumption and, certainly, a new technical process. P6 application in Banias is interesting for several reasons. For example, from the angle of development flexibility: having appeared in Pentium Pro server chip, this architecture then wandered Pentium II, Pentium III, Celeron family, and, at last, server Xeon.

Pentium 4, in its turn, is based on another architecture conditionally named P7 that is now being actively promoted by Intel. Company announced it to appear in notebooks and Celeron line next year.

Naturally, Banias will absorb new technologies absent in Pentium III. One innovation is an original approach to code processing, in particular, concerning repeated identical calculations. Banias's energy saving capability of disabling circuits unused at the moment has also proved to be true.

The September message that Intel gathers developers specially for Banias project was not accidental: the trend of economical processors has left frameworks of mobile personal computers for a long time already. It is indicative that new roadmap features Banias both as mobile, and server chip. We shall likely see a serious stresses displacement in this field closer to 2003.

However, the idea of disabling unused processor circuits occurred not only to Intel engineers: on this forum IBM presented a development novelty - PowerPC 405LP processor consuming as announced 10 times less energy than competing chips. Besides low power consumption, IBM also announced that PowerPC 405LP is optimized for such specific tasks as speech recognition and data encoding. Just at the beginning of forum Microsoft, IBM, Intel, Philips, and SpeechWorks announced a joint enterprise on creating a "base" for voice-controlled Internet applications development. We'll, probably, see some standards in this field at last instead of nowadays' isolated incompatible applications.

However, new PowerPC 405LP is initially aimed at PDA-scale devices instead of notebooks, where Intel may feel like a king of the hill at present: bunches of announcements of new PDAs with Intel's StrongArm SA-1110 processor actually prove this. Certainly, it is necessary to note it's not just Intel's merit. A new processor got appreciable help from the "good old" Microsoft. As it's known the new version of Microsoft Pocket PC 2002 operating system is focused on StrongARM support, and Hitachi SH-3 and MIPS processors somehow "dropped out" from the support list. So, we'll hear much and enough about Wintel platform for pocket PCs...

The present StrongARM PDA processor is only a development stage mostly passed for Intel. Much was said about XScale - a new generation of pocket PC processors, but that's also not a company's "horizon". On the same MPF British ARM presented idea of development of a new 64-bit processor for pocket PCs codenamed Jaguar featuring technologies more suitable for servers; however, it is oriented on a new PDA generation as well as wireless devices working with third generation (3G) mobile networks. New Jaguar features superscalar architecture that still doesn't increase power consumption or processor sizes. Extension of data trunk and address space to 64 bits, superscalar core performing more than one instruction per step will allow to increase the general productivity processor core. 64 bit should also have a good effect on streaming video and voice recognition. Certainly, Intel will become the main apologist of the new architecture as always.

The pocket PC direction is still more interesting for this company: it's known that in the first half of the month it has even announced the decision of gradual ceasing its Connected Products Division consumer electronics branch that releases digital cameras, audio players, and toys. According to company representatives this business appeared not very profitable, and now Intel is much more interested in making same StrongArm processors for pocket PCs, for example, rather than producing home devices.

The next MPF's highlight was the announcement of 64-bit architecture of Hammer family processors by AMD. Pity, there were no unexpected or special revelations during the forum: those keeping an eye on x86-64 architecture's documentation regularly published by AMD on http://www.x86-64.org/ web-site specially created for developers of software based on this architecture, perhaps, have not found anything new in the presentation.

Hammer ideology is constant: keeping full compatibility with existing 32-bit software to provide smooth and less painful transition to 64-bit calculations. Strangely enough, but right in the story about new Hammer family, AMD mentioned a new PR-ideology called True Performance Initiative and underlined that Hammer architecture will be "served" with QuantiSpeed as well, that is with newly appeared PR-ratings.

As it was underlined, AMD is going to provide execution of both 32/64-bit code with peak efficiency without productivity losses in case of 32-bit applications. The general idea of Hammer program model emphasized by AMD is that its new x86-64 instruction set is a direct heir of x86 set supplementing and expanding its 48-bit address and 40-bit physical space and adding eight new integer registers, full support of SSE/SSE2 instruction set, and so on.

The code processing model was announced to absorb the best of CISC and RISC models, in particular, on the base of CISC models, RISC-like instructions processing through Application Binary Interface, ABI, will be used.

I'll also mention the decision to use integrated DDR memory controller that, for example, will allow to fill eight-processor systems up with 128 GBytes of memory (64 DIMM sockets total).

Pleasant news for AMD: as it was found out, Microsoft had nevertheless agreed to support X86-64 Hammer architecture and MSDN library already features such interesting parameters:

[in] Specifies the architecture type of the computer
for which the stack trace is generated.
This parameter can be one of the following values. Value Meaning
IMAGE_FILE_MACHINE_I386 Intel (32-bit)
IMAGE_FILE_MACHINE_IA64 Intel (64-bit)

It's not a secret that originally Microsoft was rather cool about X86-64 64-bit architecture, and AMD & partners was for a long time engaged only in porting Hammer instruction sets to platforms such as GNU/Linux, FreeBSD and NetBSD. The support of Hammer processors in new versions of Windows is a powerful enough contribution from Microsoft into AMD's authoritativeness growth.

Probably, someone counted on rumors and expected AMD representatives to easily unveil prototype of the new processor at architecture presentation by waving a hand. Pity, sketchy rumors from Dresden say that the "live" chip is not still present. So, there is nothing to say about processor's pinout, etc.: just papers. Seems that we may forget about samples of Hammer processors until the second half-year of 2002.

VIA's report looked good on MPF. The report of Centaur Technology, a subsidiary of VIA Technologies, accentuated not processors' productivity, but, first of all, low chip cost as the general company's modus operandi. As it has been underlined, VIA is mainly aimed at markets of developing countries and has absolutely other priorities rather than leaders like AMD or Intel. VIA's motto at the present is reducing total of system instead racing for megahertz.

However, the company has its reasons to be proud: present C5A or "Samuel" is being gradually replaced by C5B or "Samuel 2" with clock rates higher than 800 MHz. Ezra or C5C originally expected as 0,15 micron and little later as 0,13 micron will appear in 1 GHz variant already by the end of this year. C5M or Ezra-T already sampled and differing from the usual 100 MHz FSB Ezra by 133 MHz FSB will also be accessible up to Christmas.

Right at the beginning of 2002 shippings of C5N processors with 900 MHz - 1,2 GHz clock rates will start. There was a very interesting statement from the company - it had decided to delay production of processors with C5X core until second half of 2002, motivating this by updating roadmap with C5W core and more careful study of C5X core. As it is known C5X will have not 12 but 16-step instruction processing conveyor, MMX and SIMD streaming instructions processing blocks, complete and working at full frequency FPU block, 256 KBytes of L2 cache, etc. C5X core will appear in two variants: C5XL and C5YL varying by sizes of cache and crystal. Expected clock rates of the first C5X are 1,1-1,3 GHz, those of C5XL - 1,2-1,5 GHz.

VIA's mention about the development of a new processor that will be almost a clone of Pentium 4 was a little sensational. New CZA will feature the same concepts as Pentium 4 chip: the same trunk, 18-level conveyor architecture. "Clone" will be manufactured on 0,10 micron technology, expected clock rate - 2 GHz and higher to 3 GHz. To some assumptions the new processor will be compatible with Socket 478. Manufacture launch is expected in 2003-2004 according to VIA managers.

It's, certainly, OK, but still there is a question of trunk R4 licensing by VIA from Intel. In conditions of present patent war of companies and taking into account Intel's already traditional suspicious attitude to all VIA's products... There is, certainly, an opinion that "Intel vs VIA" is marketing of both companies in the greater degree. However, the number of cross actions brought to courts for last two months in several countries at once, nevertheless speaks that sooner or later someone will pay for these serious acts. At least, lawyers of both companies feel confident already now - decent fees are guaranteed at least for the next year.

Information from Transmeta is inconsistent: despite unprofitable quarter results, delay with TM5800 release along with continuous rumors about possible company purchase by leaders like VIA or AMD, Transmeta had power to announce the new Crusoe TM6000 processor on MPF with integrated graphic core. Probably, it's the evolution of Crusoe TM5800 only expected in mass production, though the company insists that "Crusoe TM6000 is more economical in comparison with Crusoe TM5800, it supports LongRun power saving system and includes graphic core, north and south bridges ".

Crusoe TM6000 shippings are planned to the second half of 2002, the initial model is promised with 1 GHz clock rate. Worthy for a forum, as a whole: smoothing the impression of TM5800 delay and it's noticable that Transmeta does not stand still. It lack just one thing: to produce new TM5800 in mass amounts by November. Such news could support Transmeta's shaken authority.

Compaq reported plans of Alpha processors release. At least until 2004 it is responsible for development of 64-bit Alpha line. Due to new operating conditions Compaq had to confirm unconditional support of Itanium architecture, however, Alpha's story is not completed with its purchase by Intel and forum unveiled technical details of further platform development, in particular, details about Alpha EV7.

EV7 implementation with initial 1,2 GHz clock rate is planned to the third quarter of 2002. The new core will be equipped with 1,75 Mb of 7-level L2 cache with error correction, up to 20 GBytes/s system bus bandwidth. The core also will be equipped with a couple of built-in RDRAM memory controllers.

Some details about new PowerPC G5 were said by Motorola in its turn: its PowerPC 8500 features 10-step conveyor, new structure of internal processor bus, altered and modified NPU and FPU. Besides, processor will appear in 32-and 64-bit variants on Motorola's new HiP7 process (0,13 micron, 7 layers of copper, SOI, dielectrics with low k coefficient). A serial chip sample will not, most likely, appear up to the end of the year. Chip will cost $575 for 1,2 GHz and $695 for 1,6 GHz version, but these are just preliminary calculations.

Besides the super economical PowerPC 405LP, IBM presented the first "gigahertz" PowerPC on the forum. First, PowerPC 750FX will appear already this year with 750 MHz clock rate, but it will raise up to a gigahertz and higher in subsequent versions. The chip will become the first created by IBM with the new 0,13 micron CMOS9S technical process.

PowerPC 750FX features all technological novelties: copper wiring, SOI technology, modern low-capacity dielectrics. All these innovations joined together considerably reduce energy consumption that will allow to raise clock rate at least up to 1 GHz and the power consumption will make only 5 W. The first 750FX samples should appear in January, and it will be aimed at network equipment.

Another PowerPC from IBM - codenamed "Sahara" with 700 MHz - 1 GHz clock rates that will obviously shift Mac processors balance not for the benefit of Motorola with its PowerPC G4.

Sahara will come to replace G3 processors used in present iBook and iMac lines. It is expected that Sahara processor will be constructively made with use of copper connections and SOI; such combination of technical process still used only in PowerPC processors made for Unix servers.

According to preliminary data Sahara's architecture will be similar to AltiVec from Motorola ("AltiVeclike acceleration"), however, AltiVec coprocessor won't be required.

Mass shippings of Sahara are expected only in 2002, and shippings of small parties to interested OEM-manufacturers are expected to begin in November. Besides Apple, the new processor interests Epson, Kyocera and Nokia that ordered Sahara preliminary.

Hewlett Packard's report on MPF was interesting as well: the company unveiled details about its new PA-8800 RISC server processor that will include two PA-8700 cores and provide SMP, to put it mildly, without additional requirements.

The processor will appear with initial clock rates of about 1 GHz and with 35 MBytes of total L1 + L2 cache volume: two 750 KBytes L1 cache blocks for data and instructions for each core - 3 MBytes total, plus 32 MBytes L2 cache located outside the chip, but in the same processor module configured from four 72 Mbit EMS "1T SRAM" (one-transistor SRAM) or ESRAM chips. HP PA-8800 RISC is supposed to be made with use of copper and SOI with 0,13 micron 8-layer technical process.

I'd like to finish with MPF 2001 with a not absolutely "processor-like" forum event: TRANSTIVE TECHNOLOGIES company showed Dynamite software platform capable of translating binary code from one processor to code of another that was shown during the forum when the code of PowerPC was executed on... Athlon.

At presentation company representatives said that the essence of process is dynamic "on-the-fly" transformation of code of one architecture to code of another. The given system with Athlon processor, for example, known to support x86 instruction set perfectly worked OS Linux for PowerPC. Just miracles! Dynamite, according to company representatives, is actually a "decoder" of input commands, core coder, and translator to output code. It is something like Code Morphing Software (CMS) made by Transmeta company for its Crusoe processor. Frankly speaking, the latter is only about transformation of x86 instruction set to internal VLIW-words.

Interest to such designs is reasoned: if x86 processor can perform as PowerPC why, for example, MIPS processor can't work as StrongArm? And if to record to such software to ROM? So, with certain approach the company can have good dividends from the development and also inject new life into many present processor development.

But enough. Having spoken about developers plans, now it is time to recollect what really appeared in shops during October.

The unconditional "scandal" leader of the month is the release of new Athlon processors with Palomino core for desktop computers by AMD. Seems nice: a core new for desktop personal computers, new clock rates, but it wasn't enough for AMD: to exaggerate the pomp the company announced QuantiSpeed doctrine.

The term QuantiSpeed and the slogan "Performance Matters More Than MHz" are to explain the buyer why, for example, 1,53 GHz Athlon XP sold as Athlon XP 1800+ works faster than 1,8 GHz Thunderbird could do if it existed. It's the essence of such processor naming and new QuantiSpeed marketing ideology. Moreover, according to AMD, the ideology was only announced and wide application of this actually productivity rating is planned to 2002. Now we can expect any CPUs with Palomino core, not only desktop - mobile Athlon 4s, server Athlon MPs marked QuantiSpeed.

However, it was actually so: four processors for desktops - Athlon XP 1500+, Athlon XP 1600+, Athlon XP 1700+ and Athlon XP 1800+ were followed by announcement of new processors for multiprocessor systems - Athlon MP 1500+, Athlon MP 1600+ and Athlon MP 1800+, according to new QuantiSpeed doctrine.

Probably, AMD expected some raised interest to novelties with new "old" PR-markings. But nobody could expect such scale of ballyhoo and hot discussions around this advertising trick. However, scandals are to draw attention to products, and according to comparative productivity readouts new Athlon XP CPUs are really quite good and adequately compete with Pentium 4 top-models in the majority of tests.

The main "unblocked" move is the immediate processor shippings and sales on the wave of raised demand for the first days. According to price-lists of many leading suppliers, the entire new Athlon XP line is already available. And additional discounts scheduled almost to the end of the month only warmed consumer interest and will unequivocally increase volume of Athlon XP sales in November.

Besides, in October AMD announced 1,1 GHz Duron with Morgan core for desktop PCs supporting 3DNow! Professional technology and also announced phasing out 850 MHz and 900 MHz Duron models with the old core to give room for the new Morgan core.

At Intel had announced a whole constellation of novelties right at the beginning of this month: 12 new mobile processors including 0,13 micron Mobile Pentium III-M with Tualatin core, 512 KBytes L2 cache and 1,2 GHz clock rate; 733 MHz, 750 MHz, and 800 MHz Pentium III-M LV models; 700 MHz Pentium III-M ULV model, 650 MHz Celeron LV model, and five 733 MHz - 933 MHz Celeron models.

And Intel gradually began to deliver 1,13 GHz and 1,2 GHz Celerons for desktop PC.


  • Intel seems to be late for Christmas holiday sales and new 2,2 GHz Pentium 4 on such expected Northwood core will see the light only in the beginning of the next year
  • AMD will present only Athlon XP 1900+ before the New Year. 2000+ model will appear only in 2002
  • Enero 64 - what's that? Nothing but a new trademark registered by AMD. Seems clear it's about 64-bit products of Hammer family. As it's known, "Enero" is spanish for "January". What do they mean? What January are they talking about - 2002, 2003? In other words it seems like another intrigue.


The patent suit between Intel and VIA that begun in September with mutual recriminations in every sins possible was updated with new actions from both sides in October. Nevertheless, VIA P4X266 chipset is present in the market, and boards on it have already appeared. Motherboard manufacturers still grumble: there's no expected demand for products on the new chipset, whether due to distributors that are rather afraid of Intel's anger, or due to competing chipsets - it's not clear.

VIA amazes with further plans: the company, despite Intel protests gets ready to release still new and new Pentium 4 chipsets: for example, P4X333 (FSB 400/533/667 MHz, AGP 8x, V-LINK 8x, DDR333) will appear in the beginning of the first quarter of 2002, mass production is planned to the end of the second quarter of 2002. Other chipsets roadmaps were updated: P4X266A and P4M266A will support 533 MHz FSB, P4M333 will be equipped with Savage4 instead of Zoetrope graphic core.

However, that's not all. Who other than VIA will take care of sales of boards on the chipset? Therefore the company announced the creation of new VIA Platform Solutions Division (VPSD) that is promised to push so-called "firm" or brand VIA's platforms to all market segments from desktops to workstations and servers. VPSD will take part in development and release of motherboards with "VIA" label along with Internet tablets, TV play stations and other similar equipment.

But these are just plans for now. Probably, we'll soon see motherboards developed by VIA itself. And now, among nine boards already announced, for example, there are two being released by Soltek, but relabelled as VIA products still recognized without effort.

A master enough marketing stroke: now manufacturers won't need "white boxes" any more for P4X266 boards shippings. Certainly, those agreed with VIA.

It is already known that VIA is aimed at raising volume of "its" boards sales up to 1 million per month to the second half of 2002 that may level it with ASUS, ECS, MSI, and Gigabyte. Now this value sounds rather doubtfully, but who knows what it will be in the middle of the next year.

In the middle of October before MPF, there were messages on some changes in Intel chipset roadmaps. Among new names are, for example, Granite Bay chipset (128-bit DDR333/266, AGP 8X) and Plumas 533. Some names of other novelties changed as well: Rambus's Tulloch (i855) chipset is now Tehama-E (i.e. based on i850). It actually means that Intel decided to stop the development of Tulloch chipset with 4-bank Direct Rambus DRAM memory support for Pentium 4. Instead of Tulloch the company will present the updated version of i850 Direct RDRAM chipset with advanced I/O hub supporting workstations and High-End personal computers. If Intel doesn't change the decision, Tulloch rejection may kill 4-bank Direct RDRAM that should have become a direct competitor to DDR memory due to lower costs.

The release of 2,53 GHz Pentium 4 version planned to the third quarter obviously means FSB 533 MHz. Chipsets such as Brookdale-E, Tehama-E and Brookdale-GL planned to be released at the same time will definitely support the same bus, but Tehama-E will accordingly work with Rambus memory, and Brookdale-E and Brookdale-GL - with SDRAM/DDR.

Right at the end of the month there were messages that Intel is going to launch mass shippings of Brookdale-D/845D DDR SDRAM chipset (or "845 B-step", as it is named) in November for the official wholesale price of $42. According to the majority of leading Taiwan system board manufacturers, shippings of 845 B-step solutions will not exceed 10% of total shippings for November. In December some manufacturers are going to raise the 845 B-step/845 produced boards ratio to 50/50%, and in the beginning of 2002 Brookdale SDRAM version may cease to exist very quickly.

SiS 645 is in a very good position now without any legal problems with Intel unlike P4X266. Motherboard manufacturers met SiS645 rather friendly along with its SiS650 variant with integrated SiS315 graphic chip. Elitegroup is already close to launch mass shippings of SiS650 boards, other manufacturers are going to present similar solutions closer to the middle of November as the price difference between SiS645 and SiS650 is less than $10.

ALi is very unclear with its Alladin P4: the chipset seems to be ready, but there are no real boards on it.

Intel at the end of the month announced seven various "building blocks" for servers, including boards, modular "chassis", etc. intended for OEM system integrators. The new line of boards and chassis is designed for new processors Pentium III with 512 Kb cache.

The general news from AMD is the termination of the first available DDR chipset - AMD 760 (i.e. AMD 761 north bridge usually combined with VIA 686B and less often with AMD 766).

AMD considers that the chipset has completed its mission and may "rest in peace" now. Maybe they are right, but this chipset shows very good results in performing complex workstation tasks even in comparison with novelties. Seems like motherboards on AMD760 (Abit KG7, Asus A7M266, DFI AK76, Epox EP-8K7A, Gigabyte GA-7DX and MSI K7 Master) will soon become rarities.

The today's favorite is VIA KT266A chipset, however SiS with its SiS735 is not going to surrender the low-end market sector without a fight. Besides, new SiS745 presented right at the end of the month features fixed SiS735' defects, added DDR333 and IEEE1394 support that should bring even more competition to Socket A chipsets market. Having its own factories, SiS offers SiS735 for the wholesale price of $16 that is a buck less than the price of VIA KT266A chipset, and new SiS745 chipset supporting DDR333 memory is being shipped just for nothing - $17 - a buck more than for SiS735.

The next pleasant surprise for system boards manufacturers is the release of SiS740 chipset costing $26-$28 that will help to lower board production cost price due to the integrated graphic chip (ubiquitous SiS315).

Acer in past month has announced a new version of ALiMAGiK 1 or ALi M1647 MAGiK1 stepping C1 chipset, supporting new generation AMD Athlon XP chips with QuantiSpeed architecture (up to 1800+). It's hard to speak about prospects of the new chipset version as the company hardly restores reputation after previous not so successful DDR chipset.

And some "guiding light" at last - a new AMD760MPX chipset, boards on which have been already announced by TYAN, Gigabyte, MSI, EpOX, and others though the chipset is not officially announced yet.

AMD760MPX consists of AMD762+AMD768 bundle that will allow board manufacturers at last to produce a complete 64-bit bus between north and south bridges. Besides, AMD768 supports two external AC'97 codecs, 6-channel sound, and slot ACR. AMD762 supports up to seven PCI slots. Boards on this chipset are expected in mass amounts in November.

Memory products

Let's begin with some unpleasant events. This branch condition is rather pitiable on the whole. Even on the gloomy background of entire industry, memory products manufacture is unprofitable as never. So, everybody waste nerves and this situation is likely to remain the next year. Overproduction is one of the main branch problems that will pursue manufacturers the next years. However, if companies agree upon reduction of manufacture volumes, prices stabilization will become possible already in the second half of 2002. This will be also stimulated by the fact that due to absence of circulating assets many simply cannot spend money for fab building and next year will not simply withstand more successful competitors now building modern factories. What to do in conditions of DRAM manufacture redundancy? There are some recipes.

Winbond now tries to find niche products and to reorient manufacture to the most profitable chips. The company plans to enter some new "non-PC" markets that allow to sell products beneficially and not thrice below the price cost.

Fujitsu, after another unsuccessful quarter and reduction of 4,5 thousand workers, plans to try itself in developing software and consulting and to reduce memory products production.

Powerchip, having rather advanced factories, wants to engage in contract chip manufacture and to slightly deviate from DRAM.

Toshiba will most likely sell its division to German Infineon and be off with it.

There are other variants of a survival as well. For example, to call dumping competitors to account. Besides Micron, nurturing plans to crack down on Hynix that, according to all available information, is trying to get out of a terrible financial minus and dumps memory for minimal rates, such idea also visited four leading Japanese DRAM manufacturers during the last month. NEC, Toshiba, Hitachi, and Mitsubishi addressed to the Japanese government with the complaint about dumping policy of Korean rival companies. The complaint will be registered against Samsung and Hynix. If Japanese authorities consider given information powerful enough, then they together with Ministries of Trade, Economy and Industry will check the situation to specify, whether Korean companies are guilty, or memory prices reduction is caused by world market's general pitiable condition.

Hynix, being accused from different directions in dishonest business, first of all, due to financing by semigovernmental banks, has just awful state of affairs. Since January Hynix reduced the staff by one third and plans to dismiss 20% more workers. Within the framework of restructuring, in other words, for the sake of financial situation, Hynix sells minor actives - two LCD displays manufacture divisions, Maxtor's shares; i.e. just everything.

Samsung, by the way, is also dissatisfied with Hynix behavior. According to it, insolvent DRAM suppliers sell products for knock-down prices and OEM-companies buy them instead of building relations with suppliers that will likely survive during next years.

Micron is known to have accused Samsung itself in dumping some years ago, however, at present the company is cleared of all charges as the debt to share capital coefficient was lowered from 200% to 20%, that is a level of many USA companies.

Taiwan suffers as well. If any DRAM market participant will try to leave it, it may cause a chain reaction leading to growth of unemployment rate and impacting bank creditors of that participant that, in its turn, may shake all Taiwan economy. Therefore, such situation may need actions from Taiwan government according to "Hynix scenario".

Seems like it won't do without loud and, probably, scandalous news in DRAM market in the near future: one should possibly expect companies purchases, sales, mergers, etc.

But let's put finances aside and speak about memory as such.

Rambus's announcement of long promised Yellowstone data transmission technology on Rambus Developer Forum 2001 became a considerable event of the month. As it was found out, Yellowstone or Yellowstone Octal Data Rate (ODR) will provide bandwidth up to eight data bits per clock that is achieved by differential signal paralleling at 3,2 GHz frequency.

Yellowstone technology is based on Differential Rambus Signaling Levels (DRSL) protocol with voltage swing of 200 mV (1,2 V - logical 0, 1,0 V - logical 1), including on-chip termination and bidirectional signaling.

Octal Data Rate technology is based on multiplication of external system driving signal of 400 MHz by 4 times on the chip and increases clock rate of memory chip from 400 MHz up to 1,6 GHz.

Taking into account technology of data transmission on both clock edges, it allows already about 3,2 GHz. Phase-locked-loop frequency control circuit stabilizes synchronization and keeps random emissions at the level of up to 30 psec at such chips' productivity at the level of 6,4 GBytes/sec.

Still nobody is ready to present such technology - bus of the same Pentium 4, for example, is limited to 4,2 GBytes/sec bandwidth. Rambus, however, considers that by 2005 there will be many applications requiring 6 - 7 GBytes/sec bus bandwidth - for example, the same Sony Playstation III or communication devices.

This month was intense enough for Rambus. Not only because Intel gradually terminate cooperation with this company and reduces plans of RDRAM use in future products. Then Cisco, one of the main Rambus's clients, has refused to use its memory for the benefit of FCRAM (Fast Cycle RAM) from Fujitsu and Toshiba, and RLDRAM from Infineon. In addition, Federal Trade Commission of USA became seriously interested in Rambus's activity, mainly in relations of Rambus and JEDEC. The commission is interested in Rambus's participation in JEDEC open standards development, mainly, in 1991 - 1995.

And another court examination is almost at hand - on December, 7 Rambus will again be at law with Infineon.

Month was marked by release of final specifications of QDR (quad data rate) memory architecture - QDRII and Double Data Rate (DDR) II, promoted by Cypress, Hitachi, IDT, Micron, NEC, and Samsung.

Working at up to 333 MHz clock rates, QDRII and DDRII products (QDR Burst 2; QDR Burst 4; DDR common I/O, Burst 2; DDR common I/O, Burst 4 and DDR separate I/O, Burst 2), according to developers' plan, should become standard of high efficient memory of the second generation (2G) for network switches, routers, etc.

Now about new memory products actually appeared this month.

AMD presented MCP chips for mobile phones and other ultra portable devices. They are coupled 16, 32 or 64 Mbit flash-memory chips with 2, 4, or 8 Mbit of static SRAM.

Cypress and Ramtron released SRAM modules with the largest known capacity of 72 Mbits. New SRAM modules were created on the basis of Enhanced SRAM (ESRAM) one-transistor technology, developed by Enhanced Memory Systems, the subsidiary of Ramtron, and became part of burst SRAM series with No Bus Latency (NoBL), shipped by Cypress.

This month Intel presented the first samples of NOR flash-memory chips made with 0,13 micron technical process. New chips featuring Advanced+ Boot Block technology were designed for 3 V supply voltage and will be produced in 32 and 64 Mbit variants.

Samsung went noticeably further in new technologies implementation and announced in October the launch of the first line for producing 300 mm plates with 0,12 micron technical process. The line will produce both usual memory, and 512 Mbit chips, and by 2003 Samsung is going to be the first to transit to 0,1 micron and to mainstream 512 Mbit chips.

Infineon actually follows Samsung's heels: it has launched mass production of 256 Mbit memory chips with 0,14 micron technological norms and has already shipped samples of 512 Mbit chips to strategic partners.

The new process was implemented to 200 mm Dresden factory in the beginning of September, but mass production has started just recently. Another company's factory in Virginia, USA is set to start the new process, as well as the factory of Infineon's partner ProMOS in Taiwan. By the way, Dresden factory has already produced sample 300 mm plates. Mass production will start by the end of this year.

A little about PC2700 modules that, perhaps, were most rumored during the last months. In spite of the fact that many constructors still offer modules on preliminary tested DDR266 chips overclocked to DDR333 for impudent prices, there is still more news about real products initially designed for 166 MHz clock rate. So, 2700 DDR PC modules (128 MBytes PC2700 Unbuffered and 256 MBytes PC2700 Unbuffered DDR DIMM) from Micron, for example, have already been tested by SiS that is known to have SiS645 chipset suitable for such memory, and Mitsubishi right at the end of the month presented 2 GBytes and 1 GBytes Registered PC2700 modules on its own chips with 0,15 mm CMOS technical process. In other words, in a month or two we are likely to see mass amounts of DDR333 boards supported by appropriate memory modules.

And as the conclusion - a little about price tendencies of memory products. DRAM manufacturers threatened at the end of the summer that in case of reduction of wholesale price for "control" 128 Mbit PC133 memory chips below $1,30 factories will stop one by one, but nothing similar happened. By the middle of the month prices dipped to $1 and by its end - to $0,85 in general. Certainly, serious measures follow - court actions against each other and reorientation of manufacture to more profitable production. But now we've got what the situation allows so to say: wholesale prices, for example, for 512 MBytes RS133 modules are now at the level of $33,50, those for 256 MBytes RS133 modules - at the level of $14,80. It seems as always that it's the worst of all, and as always next week prices are much lower than previous.

DDR SDRAM was consistently cheapening during all the month, and RDRAM even became a little more expensive because Samsung had reduced production volumes of RIMM modules a little. However, in the second half of October RDRAM prices have also lowered confidently: there are lots of chips and the demand for RDRAM boards is not so great for overestimating prices artificially.

And something to brighten memory products news: Thermaltake's October novelty for "overclocking maniacs".

Thermaltake decided to equip its radiators for memory modules with additional coolers. I must admit the result is quite nice...

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