The overall performance of a computer system mainly
depends on three components (if you don't take into account hard
discs): a processor, memory and a video system. Each one affects
productivity in particular applications. But what if the performance
of these components is so great that a bus connecting them fails
to operate so efficient? Exactly this issue made the manufacturers
to change the PCI bus specs. This bus is a bottleneck now in lifting
the overall performance. The developers are currently working on
new standards on system buses so that they can be realized in 2
years. Some specifications are already finished, and soon you will
see products based on them. Of course I mean Arapahoe and HyperTransport
technologies which are meant to replace the PCI bus which is not
able to meet the up-to-date requirements anymore.
The problem of increasing a PCI bandwidth (Peripheral
Component Interconnect) has been being faced for a long time already.
The AGP specification is aimed at a higher performance by a faster
transfer of graphics data. The ISA bus has already completely delivered
its functions to the PCI one. Some functions are, however, implemented
by the USB bus (Universal Serial Bus).
A modern system bus means, first of all, a good
protocol which controls data exchange. Increasing of processors'
clock speeds, development of such memory types as DDR RAM and Rambus
with a higher bandwidth has contributed into computer operation.
A bus is no more able to manage such loads and, therefore, doesn't
allow the performance grow at the expense of a processor, video
card and memory.
You can see how the priorities of the industry
of high technologies change. When Intel and AMD optimized their
CPUs, they turned to the chipsets. The next was memory. It resulted
in Rambus DRAM and DDR RAM specifications. After that they tried
to lift the system memory bandwidth. Later we will see which architecture
will finally win.
A problem of increasing the bus bandwidth was earlier
dealt with by an unprofitable organization PCI Special Interest
Group (PCI SIG) which implemented development, realization and support
of the PCI bus. Today there are two groups promoting their own standards.
The first one - HyperTransport Technology Consortium (HTTC) is headed
by AMD. It promotes the HyperTransport standard. The other group
headed by Intel, Arapahoe Working Group promotes the Arapahoe standard
which is meant to replace the PCI-X bus (see Table 1). The competition
between these two has extended from the processor and chipset markets
to the bus architecture sphere. Currently these standards are positioned
as open, but the situation can change. If an open standard turns
into a closed one, the components makers will have to make payments
under the licence agreements.
Processor makers won't let these standards pass
by. First of all, the specification will bring a lot of money on
conclusion of the licence agreements. And secondly, optimization
of the architecture for their CPUs will let to play more successfully
on the processor market. But there can arise more problems than
advantages. According to Gabriele Sartori, President of HyperTransport
Technology Consortium, promotion of the Arapahoe by Arapahoe Working
Group and of the HyperTransport by HTTC can result in dividing the
computer market between these architectures.
Table 1. Companies which form the groups
supporting the Arapahoe and HyperTransport standards
- API Networks
- Cisco Systems
- NVIDIA Corporation
- Sun Microsystems
In fact, such situation might result in the fact
that components makers will support a platform of only one giant
(one chipset will obviously support either one or the other bus),
and therefore, will have to refuse from the other. A video card
from NVIDIA designed for the HyperTransport bus won't be compatible
with an Intel's platform or will require an adapter. This might
lift the price of a computer system and even reduce the overall
performance. However, it is still too early to speak about an equal
struggle of the architectures. AMD is ready to release products
with the HyperTransport support this year. Intel hasn't finished
the development works, and the Arapahoe will be launched probably
at the end of 2003. But let me now compare the standards.
The standard of the system bus promoted by Arapahoe
Working Group is also known as 3GIO (3D Generation Input/Output).
And the group led by Intel is also called Arapahoe Special Interest
Group (Arapahoe SIG). Apart from Intel it includes Compaq, Dell,
IBM and Microsoft. These companies were also members of PCI SIG
and took part in development works on the PCI bus. Roger Tipley,
President of PCI SIG, stated that the transition from the PCI bus
to the Arapahoe one must be as gradual as the transition from the
ISA to the PCI. So, let's look at the Arapahoe bus and its advantages.
- Arapahoe is a symmetrical bi-directional bus ensuring 2.5 GBytes/s
data rate which is almost 2.5 times more than the PCI-X bandwidth
and 9 times faster than the PCI bus (The PCI speed is taken as
266 MBytes/s as an average of 133 MBytes/s for a 32-bit 33-MHz
one and of 512 MBytes/s for a 64-bit 66-MHz one).
- The technology of peripherals connection includes a host bridge
and several terminal points to connect peripherals with a switch.
A switch can be either a separate logic element or can be integrated
into the host bridge. The switch's main function is to transfer
data streams between peripherals without using the host bridge;
it is a peer-to-peer connection. Data, when transferred from one
peripheral to another, are not kept in the cache, and this allows
reducing the overall load on the system.
- The Arapahoe bus has a scalable bandwidth, unlike the PCI one.
The manufacturers can, thus, either lift the bandwith or reduce
it by changing the number of lines.
- 32- and 64-bit addressing will be supported. Each data burst
will have one out of three priority levels so that the system
can divide a data stream from peripherals according to their priority
levels and process them by turn.
- The architecture will feature 3 levels of organization: a physical
level, a data level and a transaction level. The latter one will
transfer requests for reading and recording of data from peripherals
and back and form data bursts to transfer to the data level.
- One of the advantages is DDR RAM and QDR RAM (Quadro Data Rate
RAM) support which means twice (four times) faster operation than
it was earlier.
The Arapahoe is positioned primarily as a competitor
to the architectures of AMD (HyperTransport) and Motorola (RapidIO).
The Arapahoe does not try to be a uniform bus. Louis Burns, Vice-President
and Chief Manager of Intel's Desktop Platforms Group, named InfiniBand,
IEEE 1394b (FireWire), USB 2.0, serial ATA and 1/10-Gb Ethernet
among its "mates".
The technology meant to extend the PCI bus possibilities
can fail to appear because of a tough competition in this sphere.
There are still two years before this bus will be realized on a
hardware level, and the competitors are ready to release their products
The standard promoted by HyperTransport Technology
Consortium is currently developed by 150 large and small companies.
The consortium was founded in 1997 to develop an architecture of
a system bus. A number of companies joined the consortium after
NVIDIA announced its support for its nForce chip. The most famous
members are API NetWorks, Apple, Cisco Systems, NVIDIA Corporation,
PMC-Sierra, Sun Microsystems and Transmeta (the most of them are
open architecture supporters). Let's take a gander at the advantages
of this technology in comparison with the PCI and PCI-X and with
the oncoming buses. At
http://www.hypertransport.org you can get the particulars.
- HyperTransport, former Lightning Data Transport (LDT), is positioned
as addition to the InfiniBand technology at the telecommunicational
and integrated systems market. According to HTTC, the technology
can be successfully used both in server systems and desktop and
mobile devices. As a result, the computer architecture will change
a bit. Controllers of peripherals will be connected with a HyperTransport
- Like Arapahoe, this technology allows changing the number of
signal lines, and, therefore, the number of outputs on the board
if required. This will reduce power consumption as additional
outputs require additional feeding. That is why this technology
may become widely popular in mobile systems. Besides, the HyperTransport
is also a peer-to-peer bus, i.e. it allows exchanging data between
peripherals without enabling a processor and memory. The protocol
uses a burst transfer, the bus controller is in charge of data
exchange between devices. On Figure 2 you can see how the controller
is connected in a dual-processor systems.
- The bus transfers data at 800 MHz on the front and the rear
pulse gates so that the total bus speed is around 12.8 GBytes/s
when transferring two 8-bit words per clock. Let's compare this
performance with the current technologies. As compared with the
InfiniBand bus (1.25 MBytes/s in a 4-channel realization), the
HyperTransport bus is 10 times faster, the PCI-X one (1 GB/s)
is 12 times faster, and when compared with the PCI bus (266 MBytes/s),
the HyperTransport is 48 times faster.
- Unlike the Arapahoe, the HyperTransport allows transferring
asymmetrical data streams from (to) peripherals. A symmetrical
bandwidth is not always necessary in a computer. For example,
in systems displaying graphics information, or in systems that
actively send requests to a net to receive large amounts of data.
Last month NVIDIA announced the first nForce chipset
with the HyperTransport support. The most of the consortium participants
declared that the products supporting this bus will be launched
at the end of the current month - beginning of the next one. It
means that the specification is ready for realization, unlike the
Intel's one, and some parameters are not worse or even better than
that of the Arapahoe.
Table 2. Comparison characteristics of the
Arapahoe and HyperTransport standards
||32- and 64-bit
|Estimated release date
||end of 2003
||end of 2001
We have examined only two, the most interesting
system buses from Intel and AMD. It doesn't mean that they are the
only possible candidates for a leading position in future computers.
They are just supported by the majority of manufacturers at the
moment. It is possible that the future of each system bus will depend
on the number of hardware manufacturers supporting it. Both specifications
do not differ much from each other (Table 2), but the fact that
products with HyperTransport support will appear much earlier may
become a determining factor.
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