NEC and NEC Electronics Develop World's First 32nm-Node Multi-Layer Interconnect
NEC Corporation and NEC Electronics Corporation today announced that they have successfully developed the world's first multi-layer interconnect for 32nm-node LSIs. The joint research verified the excellent performance and high reliability of the new interconnect, owing to a newly developed low-k dielectric technology based on a plasma co-polymerization technique.
In advanced LSIs, the number of interconnects between transistors increases, while the amount of space between interconnects decreases due to miniaturization. This trend leads to higher inter-line parasitic capacitance, which may cause longer signal delays. The introduction of porous low-k dielectrics such as molecular pore stacking film is one solution to minimizing parasitic capacitance. However, existing porous low-k technologies cannot provide sufficient mechanical strength and insulation reliability at the 32nm-node and beyond. NEC and NEC Electronics have developed a technology that overcomes these issues, while simultaneously ensuring the high performance and low power consumption needed for next generation network servers and mobile terminals.
Features of the new technology
- Development of a new density-modulated low-k film technology based on a plasma co-polymerization technique. The new technology enables continuous alteration of both the dielectric constant and mechanical strength of low-k films during growth by changing the supply ratio of two types of precursors -- one for forming porous film and the other for harder dielectric film -- without breaking the vacuum. This achieves sequential and selective formation of porous and rigid low-k films, for which high mechanical robustness and adhesion strength have been confirmed.
- Development of a high-precision, selective, dry-etching technology for fine-patterning the density-modulated low-k film.
- Fabrication of a 32nm-node Cu multi-layer interconnect with 100nm pitch (i.e. 50nm for both metal-width and spacings) utilizing the aforementioned technologies, enabling a dramatic improvement in insulation reliability (leakage current is suppressed by three orders of magnitude as compared with conventional technology) with a low parasitic capacitance (83fF/mm), confirming high-speed and low-power consumption benefits.
As the integration density of Si LSI devices increases, the number of interconnects increases, resulting in higher parasitic capacitance and undesirable power consumption levels. One approach to decreasing parasitic capacitance is the introduction of low-k films such as organic silica films (SiOCH) with low polarizability, which have already been introduced in 90nm-node LSIs. Porous low-k films (obtained by introducing pores into low-k films) have been investigated for 65nm-node LSIs to further decrease capacitance. By further advancing low-k material technology, NEC, in collaboration with the MIRAI project, developed a molecular-pore-stack (MPS) low-k film, in which sub-nanometer pores were introduced uniformly. This film was then successfully applied to 45nm-node LSI interconnects.
However, there was still a challenge that needed to be addressed before 32nm-node interconnects could be realized. In general, porous low-k films are effective in decreasing parasitic capacitance, but their mechanical strength tends to decline as the porosity increases. Therefore, porous low-k films are usually used in combination with films possessing high mechanical strength. With conventional technology, these films are deposited with different processing tools, but changing tools while the film is grown inevitably exposes the wafer surface to the air, causing residual defects between each film, and giving rise to nonideality in the insulation property.
NEC and NEC Electronics' new technology achieves consecutive formation of different types of films in a single step, with a single tool, without breaking the vacuum. The density modulation technology for low-k films enables control of dielectric constants and mechanical strength of low-k films by changing the mixing ratio of two types of precursors using plasma co-polymerization technology. This single-step deposition prevents creation of defects at the interface between films, resulting in a decrease in leakage current by three orders of magnitude as compared with conventional interconnects. Moreover, the mechanical strength of the new film is twice as strong as that of conventional film, while maintaining an equal dielectric constant. Simultaneously, a novel, selective, dry-etching technique with enhanced precision was developed. This technique allows sensitive detection of the density modulation of low-k films.
By combining the above achievements, a highly reliable low-k interconnect structure was realized that does not incur current leakage, despite miniaturization of the patterning dimensions down to 50nm for 32nm-node LSIs. Moreover, interline capacitance of 83fF/mm was accomplished; a level in line with that previously achieved for 45nm-node interconnects, proving successful in suppressing power consumption. In 32nm-node ULSI interconnects, integration density is equivalent to that of placing a maximum of ten thousand lines within 1mm-width.
NEC and NEC Electronics will present the results of this research at the International Electron Devices Meeting (IEDM) 2006, being held from December 11 - 13 in San Francisco, USA.
Source: NEC Corporation
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