Intel Tulsa: Over A Billion Of Transistors, 16MB L3 cache - On August 27
According to Intel's latest server roadmaps, Xeon 7100 (Tulsa) processors will be released on August 27 replacing Xeon 7000 (Paxville MP).
Xeon 7100 will become the most technically complex x86 chip with its 1,328 million transistors and 9 times the Yonah core size (~435 mm²).
These dual-core processors will feature 16MB of shared L3 cache and dedicated L1 and L2 caches. As you can see, Xeon 7100 series will include 8 processors operating at 2.5 GHz to 3.4 GHz with 667 MHz and 800 MHz FSB. 'N' models (667 MHz FSB) will be compatible with Intel's current multi-way server platform.
Intel expects the share of Tulsa to make 28% of all sold processors in this segment already in the first sales quarter, futher growing to 98% in Q2'07.
The Core 2 architecture will get to the multi-way servers segment only in Q3'07 with dual-core Dunnington and quad-core Tigerton together with Caneland platform. Then Intel will stop supporting HyperThreading in its multi-way servers.
HKEPC
Write a comment below. No registration needed!
|
|
