TI Introduces 45-nm Chip Manufacturing Process
Before the start of the 2006 Symposium on VLSI Technology, Texas Instruments unveiled details of a 45-nanometer semiconductor manufacturing process that leverages a "wet" lithography process to double the number of chips produced on each silicon wafer, increase processing performance and reduce power consumption. Through the use of numerous proprietary techniques, TI will drive the capabilities of its multi-million transistor, System-on-Chip (SoC) processors to new levels, claiming to increase performance by 30 percent while reducing power consumption 40 percent.
TI's 45-nm process leverages SmartReflex power and performance management technologies that combine intelligent and adaptive silicon, circuit design, and software to address these power management challenges. TI takes a system-level approach with SmartReflex technologies to extend the capability across an entire 45-nm SoC design, including adaptive hardware and software technologies that dynamically control voltage, frequency and power based on device activity, modes of operation and process and temperature variation.
The new TI process also supports the DRP architecture to integrate digital RF functionality in single-chip wireless solutions. This SoC approach to wireless transmit and receive functions allows TI to apply its highly efficient CMOS manufacturing infrastructure to reduce overall system cost, reduce power consumption and free up board space. Other integration options in the TI 45-nm design libraries include a host of analog components such as resistors, inductors and capacitors that allow further SoC integration of formerly stand-alone functions.
For the first time, TI will implement the use of 193-nm immersion photo-lithography to accomplish density improvements that competitors using dry lithography at 45-nm are unable to achieve. The use of 193-nm immersion tools delivers the higher resolution and corresponding smaller device features needed to maximize the benefits of migrating to a new process. 193-nm immersion tools work by placing a thin layer of liquid between the lens and the wafer to ease the process of transferring smaller circuit designs.
The company's work in this area has resulted in the development of what it believes to be the smallest 45-nm SRAM memory cell, occupying only 0.24 square microns, up to 30 percent smaller than other 45-nm memory cell devices announced to date. Memory cells are often the first development vehicle for new manufacturing technologies and provide valuable data about transistor densities that will be achieved on complete SoCs.
Other improvements in how many transistors TI's 45-nm process can support on a chip can be attributed to the use of an ultra low-k dielectric that achieves a k value of 2.5, and reduces interconnect capacitance by 10 percent. This will be TI's third-generation process technology to use low k dielectrics for reducing capacitance and propagation delays within a device's interconnect layers, and boosting chip performance.
As with its previous generation process technologies, TI will offer several optimized 45-nm recipes to address the unique requirements of each end product or application. Through adjustments to the transistors' gate length, threshold voltage, gate dielectric thickness or bias conditions, and others, circuit designers have several options for creating flexible, optimized designs.
TI's low power 45-nm offering will extend battery life in portable products, while offering the performance to handle advanced multimedia functionality in a tightly integrated design. A mid-range process will support TI DSPs and TI's high performance ASIC library for communications infrastructure products. TI's highest performance 45-nm option supports MPU-class performance.
A collection of strain techniques will enhance transistor performance and minimize leakage for all three process versions of the process, including TI's first use of silicon-germanium in its strain application.
Finally, TI is considering techniques to cost-effectively enhance performance through use of a dual work function metal gate at some point in its 45-nm technology roadmap. Options include the use of full-silicidation-of-polysilicon (FuSI), or a combination of metal plus a silicide. Currently being explored for the highest performance process, TI believes leveraging a metal gate with continued use of proven, silicon nitrided dielectrics delivers the necessary power consumption control without having to simultaneously move to new, more complex high-k materials.
TI's 45-nm process will be manufactured on 300-mm wafers in the DMOS6 facility in Dallas, Texas. The low-power ASIC design library will be available by the end of this year, with samples of the first SoC product delivered in 2007 and initial production in mid-2008.
Source: Texas Instruments
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