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Toshiba Develops Fastest, Highest Density FeRAM

Besides the 16-megabit MRAM announced together with NEC, Toshiba today announced a newly developed FeRAM Ferroelectric Random Access Memory. The new chip takes FeRAM storage to the 64-megabit level and pushes read and write speed to 200-megabytes a second.

Fabricated with 130-nanometer CMOS process technology, the 64-megabit FeRAM is based on Toshiba's chainFeRAM architecture, which significantly reduces memory cell size. It also integrates optimized circuitry designed to reduce the circuit area and squelch noise during read operation, and ECC, a high-speed error checking and correcting circuit that assures data reliability at high speed operation, even in severe operating conditions.

The key to the performance boost is adoption of burst mode for high-speed data transfers. Its successful integration pushes read and write speed to 200-megabytes a second.

FeRAM combines the fast operating characteristics of DRAM and SRAM with flash memory's ability to retain data while powered off, characteristics that continue to attract semiconductor industry attention. Toshiba will continue its R&D in FeRAM, aiming for eventually use in a wide range of applications, including high-performance mobile digital equipment and computers.

Main specifications:

  • Process: 130 nanometer CMOS
  • Density: 64 megabits
  • Cell size: 0.7191 um2
  • Cycle time: 60 nanoseconds
  • Read/write speed (bandwidth): 200 megabytes/second
  • Power supply voltage: 3.3V, 2.5V

Source: Toshiba

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