Philips Introduces Advanced Ultra-low Power CMOS Logic Family
Royal Philips Electronics introduced its family of Advanced Ultra-low Power (AUP) CMOS logic, featuring ultra-low power consumption. The AUP logic family offers more than 55 new products available in two package options, PicoGate and MicroPak.
The AUP logic family comprises single, dual and triple gate functions housed in a 5-,6-, and 8-pin packaging allowing engineers to select the exact functions they require. Additionally, translation functions enable designers to easily interface between different voltage systems The AUP family also uses the newest MicroPak technology from Philips, which allows for migration from 0.50mm lead spacing to 0.35mm lead spacing, with the full release expected to take place by Q1 2006. Furthermore, the AUP family provides higher Electrostatic Discharge (ESD) protection, making the logic devices less vulnerable to static electricity. Typical specifications for the AUP logic family are: operating voltage range 0.8V – 3.6V, propagation delays of 2.5n @ 2.5V and a Cpd = 4 pF or less.
Philips’ AUP family of logic is available in production quantities.
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