Telairity Semiconductor Launches Real-Time HD Video Architecture
Based on multiple independent vector/scalar cores, the multicore Telairity-1 architecture is specifically designed to handle the demanding computational requirements of the H.264 (MPEG-4 Part 10) HD codec. H.264 is set to supersede MPEG-2 as the standard by which HD video is compressed in the professional broadcast environment for transmission, storage, and editing, where the new standard will deliver the same or better picture quality with a lower bit rate.
The programmable Telairity-1 architecture combines five independent vector/scalar cores, a video controller, and a DRAM controller supporting an I/O bandwidth up to 5.3 Gbps in a single multicore SoC. Each vector/scalar core features four vector pipes with independent hardware, an independent scalar unit, 128KB of on-chip vector SRAM, a 4KB vector SRAM data cache, an 8KB scalar scratchpad memory, and a 32KB instruction cache. As a fully programmable chip, Telairity-1 will allow customers to modify or add new algorithms to customize or improve the encoder over time.
At a clock rate of 668.25MHz, or nine times the 74.25-MHz 20-bit video standard, the T1P2000, first product implemented on the new architecture, achieves a total sustained chip performance of 55.5 GOP (Giga operations) per second.
Packaged in the 1156-pin FCBGA package, samples of T1P2000 are available now, with production quantities available in Q4 2005. Pricing in 10,000-piece quantities for U.S. delivery will start at $425.
Source: Telairity Semiconductor
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