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NEC Develops Low Standby Leakage Technology

Two NEC Corp. units have developed technology to lower standby power for mobile devices by combining high-k technology and a body-biasing scheme. In the laboratory, the team achieved a 1.4 picoAmpare standby leakage current for NFET and 0.3 picoAmpare for PFET. The researchers claimed these are the lowest leakage current ever achieved.

The NEC researchers targeted ultra low-power technology to reduce power consumption of system-on-chip devices to 1/30 of conventional chips, enabling the design of a battery lasting 10 times longer than present systems. The new technology is the core of NEC´s "Ultimate Low Power" initiative, and it is applicable at both the 65- and 45-nm nodes.

Standby power was negligible compared to the operating power of transistors at 180 and 130 nm. In scaled-down devices, lower supply voltage reduces active power consumption but standby power consumption often increases due to higher leakage current. At 65 nm, leakage power consumption is expected to exceed active power consumption for many devices.

Therefore leakage current suppression is essential for low standby power (LSTP) devices used in low-power applications such as mobile products. The International Technology Roadmap for Semiconductors (ITRS) predicts that higher dielectric constant (high-k) material would arrive in gate insulator used in LSTPs around 2006. The NEC group demonstrated the low leakage with high-k (HfSiON) insulator film, and intends to implement the newly developed technology in its 65-nm node LSTP devices scheduled to be available in 2006.

Source: EE Times

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