HyperTransport Release 2.0 Specification officially announced

HyperTransport Technology Consortium today announced a major new release of the HyperTransport Release 2.0 Specification, so we can finally publish its exact information.

Now we know for sure that the new HyperTransport 2.0 supports three more bus speeds: the existing 1.6 Giga Transfers/second (GT/s) of Release 1.1 Specification is extended by 2.0, 2.4, 2.8 GT/s at respective dual-data rate clocks at 1.0GHz, 1.2GHz, 1.4GHz delivering a maximum aggregate bandwidth of 22.4 GB/s (on 32-bit duplex bus). Of course, the electrical protocols of HyperTransport 2.0 are compatible to the previous releases.

Another key innovation is the mapping to PCI Express added to already existing support of PCI and PCI-X. Judging by the fact that companies like Alliance Semiconductor, AMD, and PLX Technologies already ship HyperTransport-to-PCI-X bridges, I guess HyperTransport-to—PCI Express solutions won´t take long as well.

The HT 2.0 innovations base on the frequency correction technology combined with receiver part sensivity improvements. The developers believe that all this won´t require major hardware changes and won´t result in higher energy consumption.

Write a comment below. No registration needed!