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TSMC announces 35 nm transistor prototype

TSMC reported about the development of a CMOS transistor far smaller than its current analogues. It was named FinFET, as, according to TSMC, it reminds a fish fin. The development was conducted with the participation of IBM.

The length of FinFET p-n junctions doesn´t exceed 35 nm, however TSMC staff says they could improve the FinFET technology and reduce the size even further down to 25 nm, keeping its electrical parameters suitable for industry. According to developers, they already have estimations enabling to further reduce the size in the future down to 9 (!) nm. But it´s still unknown if such transistors are to feature the same electrical parameters.

In order to reduce current leakage and semiconductor heating FinFET features the second gate. TSMC is sure that double-gating provides better control and reduces leakage, allowing the transistor size to be reduced further and current to be increased.

Well, we´ve seen it somewhere else: first, diode, then triode, tetrode, pentode, etc...

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