Hitachi´s multilevel flash cell for 1-Gbit chips
After several months of honing its proprietary multilevel flash cell structure Hitachi reported plans to release 1 Gbit flash memories supporting up to 10 Mbps data transfer rate.
Hitachi first described the assist-gate-AND architecture in December at the International Electron Devices Meeting in Washington. The company hopes its chips will be used in high-end digital cameras, cellular phones and PDAs.
Instead of using Fowler-Nordheim tunneling for programming, the chip uses hot electron injection, also used in NOR-type flash memory. But to reduce write times, electrons are injected from the source side, not from the drain side like in NOR memory, thus enabling faster, low-current parallel writing. The cell writing time, that is normally about 10-4 seconds for a Fowler-Nordheim tunneling cell, is reduced to 10-5 seconds in the AG-AND cell. Fowler-Nordheim is still used for erasures.
In addition, the chip uses a four-bank configuration instead of one bank, which would enable only a 3 MB/s write speed. Hitachi reports the chip can supprot 20-MB/s write speeds, but not in case multilevel cell structure.
1-Gbit HN29V1G91 chip is housed in a 48-pin TSOP type-I package similar to Hitachi´s previous 512-Mbit flash memory chip. The novelty is pin-compatible with NAND interfaces.
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