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Motorola to unveil third-generation PowerQuicc

Today at Smart Networks Developers Forum Motorola will unveil details of new architecture of PowerQuicc, third-generation communication processor, which samples are expected early in 2003.

The company has already mentioned some features of MPC8560 PowerQuicc III like PowerPC e500 RISC core and Ocean comm logic in its roadmap. Though other details, including the RapidIO integrated comm modules technology, PCI-X, DDR SDRAM and Gigabit Ethernet ports, became a surprise.

Besides, it will be the first PowerQuicc processor utilizing SoC methodology for inner core and some bus elements, that are not strictly task-specialized. Only some elements, including the e500 core, feature complete specialization.

RISC e500 core supports up to 1 GHz clock rates, has 7-layer cache (256 KB L2 cache).

Now 8560 is being thoroughly verified. Motorola promised the chip to be fully functional by the year-end.

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