DDR-III takes shape
Last week JEDEX brought the first info about draft specs of next-generation DDR-III SDRAM.
These very provisional DDR-III SDRAM features include 800 Mbps throughput with consequent increase to 1.5 Gbps. DDR-III power requirements will also be different, making 1.2V or 1.5V (against 1.8V of DDR-II and 2.5V of the current DDR). According to Infineon Technologies, typical capacity of the first DDR-III SDRAM chips will make 4 Gbit.
JEDEC will approve final DDR-III specs closer to the end of 2005 along with the first appearance of samples. DDR-III volume production is expected in 2007.
DDR-III is expected to feature short-loop through (SLT), the signaling technique, also used in some DDR-II devices to reduce noise at high frequencies. SLT eliminates "stubs" that branch off to carry the signal from the memory bus to each module in the system. The multiple data lines are vulnerable to greater noise at the very high frequencies of new-generation memory chips. SLT connects a series of controller drivers directly with each memory module to reduce noise and signal reflection. The technique is aimed at servers to enable the addition of eight DIMMs per channel, or four times more than with the basic DDR-II configuration. JEDEC sources at the conference said that SLT is similar to the technique used in Rambus Inc.´s RDRAM. They said that SLT is based on designs that go back to 1970 and aren´t included in Rambus´ patents.
JEDEC is also drafting an addendum to the DDR-II standard that would cover 2Gbit chips expected in 2005. DDR-II specs also has been amended to double the number of memory banks to eight for 1Gbit and higher-capacity chips. The increased number of banks reduces latency and boosts memory chip efficiency. All DDR-II memory modules will use new BGA packaging because of its smaller form factor.
Source: Silicon Strategies
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