Toshiba and Sony to announce 65-nm process technology at IEDM
Toshiba and Sony together announced the development of 65-nm chip production technology. Companies spent three years and 15 billion yens ($120 million) for the work and plan to commercialize it by March 2004.
Further details will be reported at IEDM (International Electron Devices Meeting), to take place next week, from December 9 to 11. Currently we know that transistor gateways are 30-nm wide, utilizing 1-nm high nitrated dielectric with high nitrogen content. Gateway action time is 0.72 picoseconds.
The companies underline that the new technology enables to create 256 Mbit DRAM and 64 Mbit SRAM chips.
Toshiba and Sony´s development is designed for 193-nm litho tools.
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