iXBT Labs - Computer Hardware in Detail






Chaintech Apogee GT DDR2-1100 (PC2-8800)

High-speed DDR2 memory modules are manufactured practically by all memory manufacturers. Such memory used to be made for overclockers only, but with the launch of AMD Phenoms, officially supporting DDR2-1066, it can be used on the standard platform. It's limited right now. But as the Phenom family grows (clock rates, etc), some users of such processors will wish to use the integrated memory controller to the full extent. Besides, our tests prove that the game with this AMD platform is worth the candle.

The most popular memory volume for home and office computers today is 2 GB. So we are going to review a dual-channel memory kit of this very volume from Chaintech. Like all representatives of the Apogee GT series, these modules are equipped with typical comb-like heatspreaders, which resemble the proprietary Corsair DHX cooling system. However, in this case heatspreaders contact only memory chips and do not touch a PCB. Yet, these modules were barely warm during our tests. They were also ventilated by the standard boxed cooler on the CPU. Its heat sink is placed perpendicular to memory slots, which contributes to memory ventilation.

Manufacturer Information

Module manufacturer: Walton Chaintech Corporation
Manufacturer of module chips: unknown
Web site of the module manufacturer: Walton Chaintech

Module Appearance

Module Part Number

The manufacturer's web site does not explain how to decipher the DDR Part Number. There is only a short description. Apogee GT DDR2-1100 is a kit of two 1024 MB modules based on 16 FBGA chips (64M x 8). The manufacturer guarantees 100% stable operation in DDR2-800 mode with 5-5-5-15 timings at 1.8 V as well as in DDR2-1100 mode with the same timings at 2.3 V. The default mode written in the SPD chip is DDR2-800 with 5-5-5-15 timings at 1.8 V.

SPD data

General SPD standard description:

Description of the specific SPD standard for DDR2:

Parameter Byte Value Interpretation
Fundamental Memory Type 2 08h DDR2 SDRAM
Number of Row Addresses on this assembly 3 0Eh 14 (RA0-RA13)
Number of Column Addresses on this assembly 4 0Ah 10 (CA0-CA9)
Number of DIMM Banks 5 60h 2 physical banks
Data Width of this assembly 6 40h 64 bit
Voltage Interface Level of this assembly 8 05h SSTL 1.8V
SDRAM Cycle time (tCK) at maximum supported CAS# latency (CL X) 9 25h 2.50 ns (400 MHz)
DIMM configuration type 11 00h Non-ECC
Refresh Rate/Type 12 82h 7.8125 ms - 0.5x reduced self-refresh
Primary SDRAM Width (organization type) of the memory module chips 13 08h x8
Error Checking SDRAM Width (organization type) of the memory chips in the ECC module 14 00h Not defined
Burst Lengths Supported (BL) 16 0Ch BL = 4, 8
Number of Banks on SDRAM Device 17 04h 4
CAS Latency (CL) 18 30h CL = 5, 4
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-1) 23 3Dh 3.75 ns (266.7 MHz)
Minimum clock cycle (tCK) at reduced CAS# latency (CL X-2) 25 50h 5.00 ns (200.0 MHz)
Minimum Row Precharge Time (tRP) 27 32h 12.5 ns
5, CL = 5
3.33, CL = 4
Minimum Row Active to Row Active delay (tRRD) 28 1Eh 7.5 ns
3, CL = 5
2, CL = 4
Minimum RAS to CAS delay (tRCD) 29 32h 12.5 ns
5, CL = 5
3.33, CL = 4
Minimum Active to Precharge Time (tRAS) 30 25h 37.0 ns
15, CL = 5
10, CL = 4
Module Bank Density 31 80h 512 MB
Write recovery time (tWR) 36 3Ch 15.0 ns
6, CL = 5
4, CL = 4
Internal WRITE to READ command delay (tWTR) 37 1Eh 7.5 ns
3, CL = 5
2, CL = 4
Internal READ to PRECHARGE command delay (tRTP) 38 1Eh 7.5 ns
3, CL = 5
2, CL = 4
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) 41, 40 39h, 30h 57.5 ns
23, CL = 5
15.3, CL = 4
SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) 42, 40 69h, 30h 105.0 ns
42, CL = 5
28, CL = 4
Maximum device cycle time (tCKmax) 43 80h 8.0 ns
SPD Revision 62 12h Revision 1.2
Checksum for Bytes 0-62 63 D3h 76 (correct)
Manufacturerb™s JEDEC ID Code 64-71 00h, 00h Not defined
Module Part Number 73-90 - AU1G08E32-1G6P501
Module Manufacturing Date 93-94 07h, 14h Year 2007, Week 20
Module Serial Number 95-98 00h, 00h,
00h, 00h
Not defined

Two CAS# latencies are supported by SPD - 5 and 4. The first value (CL X = 5) corresponds to DDR2-800 (2.5 ns cycle time, 400 MHz) with 5-5-5-15 timings (exact values). The second CAS latency value (CL X-1 = 4) corresponds to DDR2-533 (3.75 ns cycle time, 266.7 MHz) with nonstandard timings 4-3.3-3.3-10.

That's one more situation when Chaintech modules do not officially support DDR2-667 mode, even though you can easily configure this mode manually with typical timings 4-4-4-12 at the standard voltage.

SPD revision and checksum are specified correctly. There is no Manufacturerb™s ID Code and Serial Number. And the part number specified in the SPD does not match the part number on the modules.

These modules do not support SPD extensions of the EPP standard, even though they officially support DDR2-1100 with 5-5-5-15 timings at 2.3 V.

Testbed configuration

  • CPU: AMD Phenom 9700 (Socket AM2), 2.4 GHz (200x12), B2 stepping
  • Chipset: AMD 790FX
  • Motherboard: ASUS M3A32-MVP Deluxe, BIOS 801 dated 26/12/2007

Test results

We've tested the modules in the standard mode (DDR2-800) with the main timings scheme operating at 1.8 V. Then we switched to the DDR2-1066 mode, and BIOS automatically set timings to 5-7-7-25. It should be noted that memory operated in this mode at a relatively low voltage for this frequency (1.95 V). So, we easily managed to get back to 5-5-5-15 timings by raising the voltage. However, further attempts to reduce timings without crossing the safe threshold of 2.3 V resulted in spontaneous reboots during the tests.

The next stage was to test our memory modules in the DDR2-1100 mode with 5-5-5-15 timings at 2.3 V. In order to obtain this frequency, we had to overclock the CPU a little. However, the system was stable even without raising voltages (except for the memory voltage, of course). Further overclocking required milder timings, and full stability was preserved up to DDR2-1150 frequencies. Overclocked to 2592 MHz, the CPU voltage was raised only by 0.1 V. We could still increase the frequency. So, this memory formally does not match the overclocking potential of the processor. To be more exact, it's quite sufficient for common users, who do not overclock computers much and stay within the standard CPU voltage, because further overclocking would require to raise it.

All results are obtained with the TLB patch disabled (this option in ASUS BIOS is called CPU Tweak), because as we have already noted, this patch significantly reduces performance, and we still haven't found an application or conditions where this notorious bug reveals itself. I repeat that memory in DDR2-800 and DDR2-1066 modes operates at these very frequencies on any Phenom processor (unlike Athlon 64 X2, where memory frequencies may differ, because they are specified by a divider to the CPU clock rate, and not all frequencies have corresponding dividers). It has to do with the fixed frequency of the memory controller, which can be specified separately, just like a processor clock rate. For example, the existing Phenom processors use 2 GHz as a default frequency for the memory controller (x10). As a rule, this parameter is connected to the north bridge frequency in BIOS.

  Chaintech Apogee GT DDR2-1100
Memory frequency, MHz
(DDR2 MHz)
Frequency of the integrated memory controller, MHz
(DDR2 MHz)
2000 (200x10)
2000 (200x10)
2070 (207x10)
2160 (216x10)
Frequency of processor cores, MHz
(FSB clock rate x FID)
Default memory timings, voltage
1.8 V
1.95 V
2.3 V
2.3 V
Minimum memory timings, voltage
(not tested)
up to 2.3 V
(not tested)
(not tested)
Average memory read bandwidth (MB/sec),
1 core
Average memory write bandwidth (MB/sec),
1 core
Max. memory read bandwidth (MB/sec),
1 core
Max. memory write bandwidth (MB/sec),
1 core
Average memory read bandwidth (MB/sec),
4 cores
Average memory write bandwidth (MB/sec),
4 cores
Max. memory read bandwidth (w/PF, MB/sec),
4 cores
Max. memory write bandwidth (NT, MB/sec),
4 cores
Minimum pseudo-random access latency, ns
Minimum random access latency*, ns

*block size - 32 MB

Test results demonstrate stable growth of parameters as frequencies are increased. Real memory bandwidth grows and latencies are reduced even in case of a "pure" increase in memory frequency (an upgrade from DDR2-800 to DDR2-1066, which is not accompanied by an increase in CPU clock rate). Thus, high-speed memory may be justified from the practical point of view. Memory write performance has a surprise in store for us, to be more exact, maximum memory bandwidth for a single core. It's hard to come up with a logical explanation to such a spread of results. However, there is nothing to worry about, because the average memory bandwidth is growing steadily. Its growth is again proportional to the increase in memory frequency, which is much more important in terms of the effect on performance in real applications. Peak values are purely synthetic in nature, they are interesting only for theoretical analysis of the architecture.

We should mention another practical issue. We run our tests with the integrated memory controller in Phenom processors operating in ganged mode, which provides higher results in a single core access mode, that is in tasks critical to execution speed of a single thread. But if you run multi-thread applications with equal priority, you'd better use the unganged mode.

Bottom line

Chaintech Apogee GT DDR2-1100 (PC2-8800) kit is a good choice for a slightly overclocked system on AMD Phenom. In practice, 2.6 GHz is the most popular clock rate for processors with B2 stepping, further overclocking requires a significantly higher voltage. Besides, it depends much on a given processor. Our conclusion also hints that prices for these memory modules should be practical, or users will prefer Corsair, Kingston, and other products with much higher maximum frequencies.

Dmitry Laptev (lpt@ixbt.com)
March 3, 2008

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